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HMC870LC5TR (STM-32(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

HMC870LC5TR

ADIID: C661790STM-32(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · HMC870LC5TR (STM-32(5x5))1N/C2IO233V34NC5IO26IO37N/C8N/C9N/C10N/C11N/C12N/C13IO1514N/C15IO1716ACG317N/C33GND32IO3231IO3130ACG129IO2928N/C27N/C26N/C25N/C24N/C23N/C22N/C21IO1020IO919N/C18N/CGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4NCNCNo Connect (Leave Floating)
5IO2I/OGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6IO3I/OGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
8N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
9N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
10N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
11N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
12N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
15IO17I/OGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16ACG3I/OMultiplexed I/O & Peripheral Pin ACG3 (General)
17N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
18N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
19N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
20IO9I/OGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21IO10I/OGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
23N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
24N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
25N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
26N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
27N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
28N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
29IO29I/OGeneral Purpose Digital I/O Pin IO29
30ACG1I/OMultiplexed I/O & Peripheral Pin ACG1 (General)
31IO31I/OGeneral Purpose Digital I/O Pin IO31
32IO32I/OGeneral Purpose Digital I/O Pin IO32
33GNDGNDGround Reference Pin (GND)
PIN 1 N/C
I/O
Multiplexed I/O & Peripheral Pin N/C (General)
Design note: Signal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: HMC870LC5TR (ADI · STM-32(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
HMC870LC5TR (STM-32(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
HMC870LC5TR (STM-32(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
HMC870LC5TR (STM-32(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
HMC870LC5TR (STM-32(5x5)) - 4. Package Dimensions (D×E×A)
STM-32(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
HMC870LC5TR (STM-32(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
HMC870LC5TR (STM-32(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for HMC870
P1 · p01_fig01759×417px
HMC870LC5TR (STM-32(5x5)) — Typical Applications
Typical Applications
P1 · p01_fig02810×895px
HMC870LC5TR (STM-32(5x5)) — Electrical Specifications, TA = +25° C, Vdd = 7V, Vctl = 1V, Idd = 165mA*
Electrical Specifications, TA = +25° C, Vdd = 7V, Vctl = 1V, Idd = 165mA*
P1 · p01_fig01P1
HMC870LC5TR (STM-32(5x5)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig01759×417px
HMC870LC5TR (STM-32(5x5)) — Electrical Specifications, TA = +25° C, Vdd = 7V, Vctl = 1V, Idd = 165mA* Continued
Electrical Specifications, TA = +25° C, Vdd = 7V, Vctl = 1V, Idd = 165mA* Continued
P9 · p09_fig01759×535px
HMC870LC5TR (STM-32(5x5)) — OPTICAL & MODULATOR DRIVERS - SMT
OPTICAL & MODULATOR DRIVERS - SMT
P9 · p09_fig021605×1109px
HMC870LC5TR (STM-32(5x5)) — Outline Drawing
Outline Drawing
P9 · p09_fig02P9
HMC870LC5TR (STM-32(5x5)) — Datasheet Page 9 (p09_fig02)
Datasheet Page 9 (p09_fig02)
P10 · p10_fig01759×499px
HMC870LC5TR (STM-32(5x5)) — Pin Number Function Description Interface Schematic
Pin Number Function Description Interface Schematic
P10 · p10_fig02530×490px
HMC870LC5TR (STM-32(5x5)) — RF output for amplifier. Connect the DC bias (Vdd) network to provide drain current (Idd). See application
RF output for amplifier. Connect the DC bias (Vdd) network to provide drain current (Idd). See application
P12 · p12_fig011790×1743px
HMC870LC5TR (STM-32(5x5)) — List of Materials for Evaluation PCB 108347 [1]
List of Materials for Evaluation PCB 108347 [1]

Technical Specifications & Part Details (HMC870LC5TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:HMC870LC5TR (STM-32(5x5)) is a 32-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 2.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.3V to 7V supply operation across 85C -40C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 7V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
85C -40C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 2.00 mm (A1=0.10 mm)
Package family: OTHER (STM-32(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (STM-32(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
STM-32(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HMC870LC5TR (STM-32(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HMC870LC5TR (STM-32(5x5))?

Manufactured by ADI, the HMC870LC5TR is housed in a STM-32(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.3V to 7V. Key pins include: 1 (N/C: Multiplexed I/O & Peripheral Pin N/C (General)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

What are the IPC-7351B PCB Footprint dimensions for HMC870LC5TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HMC870LC5TR (STM-32(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HMC870LC5TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HMC870LC5TR (ADI, STM-32(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & HMC870 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4NCNo_ConnectNo Connect (Leave Floating)
5IO2Digital_IOGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6IO3Digital_IOGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
8N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
9N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
10N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
11N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
12N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
15IO17Digital_IOGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16ACG3Digital_IOSignal terminal ACG3 (I/O, 3.3V to 7V domain). Multiplexed alternate functions: ACG3. Supported peripheral buses: General.
17N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
18N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
19N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
20IO9Digital_IOGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21IO10Digital_IOGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
23N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
24N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
25N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
26N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
27N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
28N/CDigital_IOSignal terminal N/C (I/O, 3.3V to 7V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
29IO29Digital_IOGeneral Purpose Digital I/O Pin IO29
30ACG1Digital_IOSignal terminal ACG1 (I/O, 3.3V to 7V domain). Multiplexed alternate functions: ACG1. Supported peripheral buses: General.
31IO31Digital_IOGeneral Purpose Digital I/O Pin IO31
32IO32Digital_IOGeneral Purpose Digital I/O Pin IO32
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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