ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH32V203C8U6 (QFN-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V203C8U6

WCHID: C6407762QFN-48(7x7) · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V203C8U6 (QFN-48(7x7))1VBAT2PC13/TAMPER_3PC14/OSC32IN4PC15/OSC32OU5OSC_IN/PD06OSC_OUT/PD17NRST8VSSA9VDDA10PA0/WKUP/ADC11PA1/ADC112PA2/ADC213PA3/ADC314PA4/ADC415PA5/ADC516PA6/ADC617PA7/ADC718PB0/ADC819PB1/ADC920PB2/BOOT121PB1022PB1123VSS_124VDD_VIO_125PB1249EP48VDD_VIO_347VSS_346PB945PB844BOOT043PB7/USB2DP42PB6/USB2DM41PB540PB439PB338PA1537PA14/SWCLK36VDD_235VSS_234PA13/SWDIO33PA12/USB1DP32PA11/USB1DM31PA1030PA929PA828PB1527PB1426PB13Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13/TAMPER_RTCI/OMultiplexed I/O & Peripheral Pin PC13/TAMPER_RTC (RTC/CLK)
3PC14/OSC32INI/OMultiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)
4PC15/OSC32OUTI/OMultiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)
5OSC_IN/PD0I/OMultiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)
6OSC_OUT/PD1I/OMultiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8VSSAGNDGround Reference Pin (VSSA)
9VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
10PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
11PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
12PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
13PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
14PA4/ADC4I/OMultiplexed I/O & Peripheral Pin PA4/ADC4 (ADC)
15PA5/ADC5I/OMultiplexed I/O & Peripheral Pin PA5/ADC5 (ADC)
16PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
17PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
18PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
19PB1/ADC9I/OMultiplexed I/O & Peripheral Pin PB1/ADC9 (ADC)
20PB2/BOOT1I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
21PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
22PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
23VSS_1GNDGround Reference Pin (VSS_1)
24VDD_VIO_1PowerPower Supply Input (VDD_VIO_1 — 3.3V / 5.0V Standard Logic)
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
27PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
28PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
29PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
30PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
31PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
32PA11/USB1DMI/OMultiplexed I/O & Peripheral Pin PA11/USB1DM (USB)
33PA12/USB1DPI/OMultiplexed I/O & Peripheral Pin PA12/USB1DP (USB)
34PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
35VSS_2GNDGround Reference Pin (VSS_2)
36VDD_2PowerPower Supply Input (VDD_2 — 3.3V / 5.0V Standard Logic)
37PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
38PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
39PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
40PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
41PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
42PB6/USB2DMI/OMultiplexed I/O & Peripheral Pin PB6/USB2DM (USB)
43PB7/USB2DPI/OMultiplexed I/O & Peripheral Pin PB7/USB2DP (USB)
44BOOT0IInput-Only Pin BOOT0 (General)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
46PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
47VSS_3GNDGround Reference Pin (VSS_3)
48VDD_VIO_3PowerPower Supply Input (VDD_VIO_3 — 3.3V / 5.0V Standard Logic)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V203C8U6 (WCH · QFN-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V203C8U6 (QFN-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V203C8U6 (QFN-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V203C8U6 (QFN-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V203C8U6 (QFN-48(7x7)) - 4. Package Dimensions (D×E×A)
QFN-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V203C8U6 (QFN-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V203C8U6 (QFN-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH32V203
P17 · p17_fig01EXACT PACKAGE
CH32V203C8U6 (QFN-48(7x7)) — V3.0 15
V3.0 15
P20 · p20_fig01EXACT PACKAGE
CH32V203C8U6 (QFN-48(7x7)) — 5 8 NRST I - NRST
5 8 NRST I - NRST
P15 · p15_fig011662×1177px
CH32V203C8U6 (QFN-48(7x7)) — PC14/OSC32IN PC15/OSC32OUT
PC14/OSC32IN PC15/OSC32OUT
P15 · p15_fig01P15
CH32V203C8U6 (QFN-48(7x7)) — Datasheet Page 15 (p15_fig01)
Datasheet Page 15 (p15_fig01)
P17 · p17_fig01P17
CH32V203C8U6 (QFN-48(7x7)) — Datasheet Page 17 (p17_fig01)
Datasheet Page 17 (p17_fig01)
P20 · p20_fig021802×1575px
CH32V203C8U6 (QFN-48(7x7)) — V3.0 18
V3.0 18
P39 · p39_fig011852×1048px
CH32V203C8U6 (QFN-48(7x7)) — 图4-5 外接8M 晶体典型电路
图4-5 外接8M 晶体典型电路
P39 · p39_fig02715×396px
CH32V203C8U6 (QFN-48(7x7)) — 图4-6 外接32.768K 晶体典型电路
图4-6 外接32.768K 晶体典型电路

Technical Specifications & Part Details (CH32V203C8U6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V203C8U6 (QFN-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
144MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.50×5.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.85 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V203C8U6 (QFN-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V203C8U6 (QFN-48(7x7))?

Manufactured by WCH, the CH32V203C8U6 is housed in a QFN-48(7x7) package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13/TAMPER_RTC: Multiplexed I/O & Peripheral Pin PC13/TAMPER_RTC (RTC/CLK)), 3 (PC14/OSC32IN: Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)), 4 (PC15/OSC32OUT: Multiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)), 5 (OSC_IN/PD0: Multiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)), 6 (OSC_OUT/PD1: Multiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32V203C8U6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V203C8U6 (QFN-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.50 × 5.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V203C8U6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V203C8U6 (WCH, QFN-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & CH32V203 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13/TAMPER_RTCDigital_IOSignal terminal PC13/TAMPER_RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER_RTC. Supported peripheral buses: RTC/CLK.
3PC14/OSC32INDigital_IOSignal terminal PC14/OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK.
4PC15/OSC32OUTDigital_IOSignal terminal PC15/OSC32OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15/OSC32OUT. Supported peripheral buses: RTC/CLK.
5OSC_IN/PD0Digital_IOSignal terminal OSC_IN/PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN/PD0. Supported peripheral buses: RTC/CLK.
6OSC_OUT/PD1Digital_IOSignal terminal OSC_OUT/PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT/PD1. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
11PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
12PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
13PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
14PA4/ADC4AnalogSignal terminal PA4/ADC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ADC4. Supported peripheral buses: ADC.
15PA5/ADC5AnalogSignal terminal PA5/ADC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5. Supported peripheral buses: ADC.
16PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
17PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
18PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
19PB1/ADC9AnalogSignal terminal PB1/ADC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC.
20PB2/BOOT1Digital_IOSignal terminal PB2/BOOT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General.
21PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
22PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
23VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
24VDD_VIO_1Power_InPrimary positive power supply input (VDD_VIO_1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
26PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
27PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
28PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
29PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
30PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
31PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
32PA11/USB1DMDigital_IOSignal terminal PA11/USB1DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/USB1DM. Supported peripheral buses: USB.
33PA12/USB1DPDigital_IOSignal terminal PA12/USB1DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/USB1DP. Supported peripheral buses: USB.
34PA13/SWDIODigital_IOSignal terminal PA13/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG.
35VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
36VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
38PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
39PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
40PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
41PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
42PB6/USB2DMDigital_IOSignal terminal PB6/USB2DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/USB2DM. Supported peripheral buses: USB.
43PB7/USB2DPDigital_IOSignal terminal PB7/USB2DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/USB2DP. Supported peripheral buses: USB.
44BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
45PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
46PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
47VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD_VIO_3Power_InPrimary positive power supply input (VDD_VIO_3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
ExplorePartsPackagesMFRsUpload