ChipDocs.org
⌘K
2284 PARTSUpload PDF
SCH5127-NW (MQFP-128(14x20)) — Symbol, Footprint IPC-7351B & 3D STEP Model

SCH5127-NW

MICROCHIPID: C639518MQFP-128(14x20) · 128 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SCH5127-NW (MQFP-128(14x20))1V1_IN2V2_IN3VTRIP_IN4VTR5nMTR06nDSKCHG7nDS08VSS9nDIR10nSTEP11nWDATA12nWGATE13nHDSEL14nINDEX15nTRK016nWRTPRT17nRDATA18CLOCKI19LAD020LAD121LAD222LAD323nLFRAME24nLDRQ25nPCI_RESET26PCI_CLK27SER_IRQ28nIDE_RSTDRV/29VTR30GP20/SPEAKER31VSS32VBAT33nINTRD_IN34AVSS35VCC36GP27/nIO_SMI37KDAT/GP2138KCLK/GP2239MDAT/GP3240MCLK/GP3341GP36/nKBDRST42GP37/A20M43VSS44VTR45nINIT46nSLCTIN47PD048PD149PD250PD351PD452PD553PD654PD755VSS56SLCT57PE58BUSY59nACK60nERROR61nALF62nSTROBE63nRI164nDCD1128+2.5V_IN127VCCP_IN126REMOTE1+125REMOTE1-124REMOTE2+123REMOTE2-122HVTR121HVSS120VID0119VID1118VID2117VID3116VID4115FANTACH1114FANTACH2113VID5112FANTACH3111PWM1110PWM2109GP17/PWM3108GP16/PWM3/nP107SDA(DDCSDA_2106SCLK(DDCSCL_105SCLK1(DDCSCL104SDA1(DDCSDA_103IO103102FCAP101VSS100nRSMRST99nPB_OUT98nPB_IN97nPCIRST_OUT196nPCIRST_OUT295nPCIRST_OUT394GP60/nLED1/W93GP61/LED292nPS_ON91VTR90GP42/nIO_PME89nSLP_S388nSLP_S587nPCIRST_OUT486IO8685n3VSB_GATE184PWRGD_3V83IO8382PWRGD_PS81GP43/nFPRST/80GP57/nDTR2/S79GP56/nCTS2/L78GP55/nRTS2/V77GP54/nDSR2/P76GP53/TXD2(IR75IO7574VSS73GP51/nDCD2/L72VTR71GP50/nRI2/PW70nDTR169nCTS168nRTS1(SYSOPT67nDSR166TXD165RXD1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.886.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4mm
2. 2D FOOTPRINT
128127126125124123122121120119118117116115114113112111110109108107106105104103102101100999897333435363738394041424344454647484950515253545556575859606162636412345678910111213141516171819202122232425262728293031326566676869707172737475767778798081828384858687888990919293949596E=14.00mm · Pitch e=0.50mmD=20.00mm-18-16-14-12-10-8-6-4-20246810121416181614121086420-2-4-6-8-10-12-14-16mm
3. 3D CAD MODEL
Package Body: 14.00mm × 20.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (128/128)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1V1_INI/OMultiplexed I/O & Peripheral Pin V1_IN (General)
2V2_INI/OMultiplexed I/O & Peripheral Pin V2_IN (General)
3VTRIP_INI/OMultiplexed I/O & Peripheral Pin VTRIP_IN (General)
4VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
5nMTR0I/OMultiplexed I/O & Peripheral Pin nMTR0 (General)
6nDSKCHGI/OMultiplexed I/O & Peripheral Pin nDSKCHG (General)
7nDS0I/OMultiplexed I/O & Peripheral Pin nDS0 (General)
8VSSGNDGround Reference Pin (VSS)
9nDIRI/OMultiplexed I/O & Peripheral Pin nDIR (General)
10nSTEPI/OMultiplexed I/O & Peripheral Pin nSTEP (General)
11nWDATAI/OMultiplexed I/O & Peripheral Pin nWDATA (General)
12nWGATEI/OMultiplexed I/O & Peripheral Pin nWGATE (General)
13nHDSELI/OMultiplexed I/O & Peripheral Pin nHDSEL (General)
14nINDEXI/OMultiplexed I/O & Peripheral Pin nINDEX (General)
15nTRK0I/OMultiplexed I/O & Peripheral Pin nTRK0 (General)
16nWRTPRTI/OMultiplexed I/O & Peripheral Pin nWRTPRT (General)
17nRDATAI/OMultiplexed I/O & Peripheral Pin nRDATA (General)
18CLOCKII/OMultiplexed I/O & Peripheral Pin CLOCKI (General)
19LAD0I/OMultiplexed I/O & Peripheral Pin LAD0 (General)
20LAD1I/OMultiplexed I/O & Peripheral Pin LAD1 (General)
21LAD2I/OMultiplexed I/O & Peripheral Pin LAD2 (General)
22LAD3I/OMultiplexed I/O & Peripheral Pin LAD3 (General)
23nLFRAMEI/OMultiplexed I/O & Peripheral Pin nLFRAME (General)
24nLDRQI/OMultiplexed I/O & Peripheral Pin nLDRQ (General)
25nPCI_RESETISystem Enable & Hardware Reset (nPCI_RESET)
26PCI_CLKI/OMultiplexed I/O & Peripheral Pin PCI_CLK (General)
27SER_IRQI/OMultiplexed I/O & Peripheral Pin SER_IRQ (General)
28nIDE_RSTDRV/GP10I/OMultiplexed I/O & Peripheral Pin nIDE_RSTDRV/GP10 (General)
29VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
30GP20/SPEAKER_OUTI/OMultiplexed I/O & Peripheral Pin GP20/SPEAKER_OUT (General)
31VSSGNDGround Reference Pin (VSS)
32VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
33nINTRD_INI/OMultiplexed I/O & Peripheral Pin nINTRD_IN (General)
34AVSSGNDGround Reference Pin (AVSS)
35VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
36GP27/nIO_SMI/P17I/OMultiplexed I/O & Peripheral Pin GP27/nIO_SMI/P17 (General)
37KDAT/GP21I/OMultiplexed I/O & Peripheral Pin KDAT/GP21 (General)
38KCLK/GP22I/OMultiplexed I/O & Peripheral Pin KCLK/GP22 (General)
39MDAT/GP32I/OMultiplexed I/O & Peripheral Pin MDAT/GP32 (General)
40MCLK/GP33I/OMultiplexed I/O & Peripheral Pin MCLK/GP33 (General)
41GP36/nKBDRSTI/OMultiplexed I/O & Peripheral Pin GP36/nKBDRST (General)
42GP37/A20MI/OMultiplexed I/O & Peripheral Pin GP37/A20M (General)
43VSSGNDGround Reference Pin (VSS)
44VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
45nINITI/OMultiplexed I/O & Peripheral Pin nINIT (General)
46nSLCTINI/OMultiplexed I/O & Peripheral Pin nSLCTIN (General)
47PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
48PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
49PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
50PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
51PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
52PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
53PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
54PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
55VSSGNDGround Reference Pin (VSS)
56SLCTI/OMultiplexed I/O & Peripheral Pin SLCT (General)
57PEI/OMultiplexed I/O & Peripheral Pin PE (General)
58BUSYI/OMultiplexed I/O & Peripheral Pin BUSY (General)
59nACKI/OMultiplexed I/O & Peripheral Pin nACK (General)
60nERRORI/OMultiplexed I/O & Peripheral Pin nERROR (General)
61nALFI/OMultiplexed I/O & Peripheral Pin nALF (General)
62nSTROBEI/OMultiplexed I/O & Peripheral Pin nSTROBE (General)
63nRI1I/OMultiplexed I/O & Peripheral Pin nRI1 (General)
64nDCD1I/OMultiplexed I/O & Peripheral Pin nDCD1 (General)
65RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
66TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
67nDSR1I/OMultiplexed I/O & Peripheral Pin nDSR1 (General)
68nRTS1(SYSOPT)I/OMultiplexed I/O & Peripheral Pin nRTS1(SYSOPT) (General)
69nCTS1I/OMultiplexed I/O & Peripheral Pin nCTS1 (General)
70nDTR1I/OMultiplexed I/O & Peripheral Pin nDTR1 (General)
71GP50/nRI2/PWM1I/OMultiplexed I/O & Peripheral Pin GP50/nRI2/PWM1 (PWM)
72VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
73GP51/nDCD2/LED1/WDTI/OMultiplexed I/O & Peripheral Pin GP51/nDCD2/LED1/WDT (General)
74VSSGNDGround Reference Pin (VSS)
75IO75I/OGeneral Purpose Digital I/O Pin IO75
76GP53/TXD2(IRTX)/VID7I/OMultiplexed I/O & Peripheral Pin GP53/TXD2(IRTX)/VID7 (UART)
77GP54/nDSR2/PWM2I/OMultiplexed I/O & Peripheral Pin GP54/nDSR2/PWM2 (PWM)
78GP55/nRTS2/VID6I/OMultiplexed I/O & Peripheral Pin GP55/nRTS2/VID6 (General)
79GP56/nCTS2/LED2I/OMultiplexed I/O & Peripheral Pin GP56/nCTS2/LED2 (General)
80GP57/nDTR2/SPEAKER_OUTI/OMultiplexed I/O & Peripheral Pin GP57/nDTR2/SPEAKER_OUT (General)
81GP43/nFPRST/VRD_DETI/OMultiplexed I/O & Peripheral Pin GP43/nFPRST/VRD_DET (General)
82PWRGD_PSI/OMultiplexed I/O & Peripheral Pin PWRGD_PS (General)
83IO83I/OGeneral Purpose Digital I/O Pin IO83
84PWRGD_3VI/OMultiplexed I/O & Peripheral Pin PWRGD_3V (General)
85n3VSB_GATE1I/OMultiplexed I/O & Peripheral Pin n3VSB_GATE1 (General)
86IO86I/OGeneral Purpose Digital I/O Pin IO86
87nPCIRST_OUT4/GP14I/OMultiplexed I/O & Peripheral Pin nPCIRST_OUT4/GP14 (General)
88nSLP_S5I/OMultiplexed I/O & Peripheral Pin nSLP_S5 (General)
89nSLP_S3I/OMultiplexed I/O & Peripheral Pin nSLP_S3 (General)
90GP42/nIO_PMEI/OMultiplexed I/O & Peripheral Pin GP42/nIO_PME (General)
91VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
92nPS_ONI/OMultiplexed I/O & Peripheral Pin nPS_ON (General)
93GP61/LED2I/OMultiplexed I/O & Peripheral Pin GP61/LED2 (General)
94GP60/nLED1/WDTI/OMultiplexed I/O & Peripheral Pin GP60/nLED1/WDT (General)
95nPCIRST_OUT3/GP13I/OMultiplexed I/O & Peripheral Pin nPCIRST_OUT3/GP13 (General)
96nPCIRST_OUT2/GP12I/OMultiplexed I/O & Peripheral Pin nPCIRST_OUT2/GP12 (General)
97nPCIRST_OUT1/GP11I/OMultiplexed I/O & Peripheral Pin nPCIRST_OUT1/GP11 (General)
98nPB_INI/OMultiplexed I/O & Peripheral Pin nPB_IN (General)
99nPB_OUTI/OMultiplexed I/O & Peripheral Pin nPB_OUT (General)
100nRSMRSTI/OMultiplexed I/O & Peripheral Pin nRSMRST (General)
101VSSGNDGround Reference Pin (VSS)
102FCAPI/OMultiplexed I/O & Peripheral Pin FCAP (General)
103IO103I/OGeneral Purpose Digital I/O Pin IO103
104SDA1(DDCSDA_5V)PowerPower Supply Input (SDA1(DDCSDA_5V) — 3.3V / 5.0V Standard Logic)
105SCLK1(DDCSCL_5V)PowerPower Supply Input (SCLK1(DDCSCL_5V) — 3.3V / 5.0V Standard Logic)
106SCLK(DDCSCL_2.5V)PowerPower Supply Input (SCLK(DDCSCL_2.5V) — 3.3V / 5.0V Standard Logic)
107SDA(DDCSDA_2.5V)PowerPower Supply Input (SDA(DDCSDA_2.5V) — 3.3V / 5.0V Standard Logic)
108GP16/PWM3/nPROCHOTI/OMultiplexed I/O & Peripheral Pin GP16/PWM3/nPROCHOT (PWM)
109GP17/PWM3I/OMultiplexed I/O & Peripheral Pin GP17/PWM3 (PWM)
110PWM2I/OMultiplexed I/O & Peripheral Pin PWM2 (PWM)
111PWM1I/OMultiplexed I/O & Peripheral Pin PWM1 (PWM)
112FANTACH3I/OMultiplexed I/O & Peripheral Pin FANTACH3 (General)
113VID5I/OMultiplexed I/O & Peripheral Pin VID5 (General)
114FANTACH2I/OMultiplexed I/O & Peripheral Pin FANTACH2 (General)
115FANTACH1I/OMultiplexed I/O & Peripheral Pin FANTACH1 (General)
116VID4I/OMultiplexed I/O & Peripheral Pin VID4 (General)
117VID3I/OMultiplexed I/O & Peripheral Pin VID3 (General)
118VID2I/OMultiplexed I/O & Peripheral Pin VID2 (General)
119VID1I/OMultiplexed I/O & Peripheral Pin VID1 (General)
120VID0I/OMultiplexed I/O & Peripheral Pin VID0 (General)
121HVSSGNDGround Reference Pin (HVSS)
122HVTRI/OMultiplexed I/O & Peripheral Pin HVTR (General)
123REMOTE2-I/OMultiplexed I/O & Peripheral Pin REMOTE2- (General)
124REMOTE2+I/OMultiplexed I/O & Peripheral Pin REMOTE2+ (General)
125REMOTE1-I/OMultiplexed I/O & Peripheral Pin REMOTE1- (General)
126REMOTE1+I/OMultiplexed I/O & Peripheral Pin REMOTE1+ (General)
127VCCP_INPowerPower Supply Input (VCCP_IN — 3.3V / 5.0V Standard Logic)
128+2.5V_INPowerPower Supply Input (+2.5V_IN — 3.3V / 5.0V Standard Logic)
PIN 1 V1_IN
I/O
Multiplexed I/O & Peripheral Pin V1_IN (General)
Design note: Signal terminal V1_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V1_IN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SCH5127-NW (MICROCHIP · MQFP-128(14x20))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SCH5127-NW (MQFP-128(14x20)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SCH5127-NW (MQFP-128(14x20)) - 2. Standard Pinout (Top View)
True package pinout (128 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SCH5127-NW (MQFP-128(14x20)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SCH5127-NW (MQFP-128(14x20)) - 4. Package Dimensions (D×E×A)
MQFP-128(14x20) · 14.00×20.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
SCH5127-NW (MQFP-128(14x20)) - 5. Recommended Land Pattern
IPC-7351B Footprint (128 Pads)Expand ›
6. Application SchematicSCHEMATIC
SCH5127-NW (MQFP-128(14x20)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for SCH5127
P1 · p01_fig01377×200px
SCH5127-NW (MQFP-128(14x20)) — Super I/O with Temperature Sensing, Auto Fan Control and
Super I/O with Temperature Sensing, Auto Fan Control and
P4 · p04_fig011782×1830px
SCH5127-NW (MQFP-128(14x20)) — FIGURE 1: SCH5127 BLOCK DIAGRAM
FIGURE 1: SCH5127 BLOCK DIAGRAM
P5 · p05_fig011779×1897px
SCH5127-NW (MQFP-128(14x20)) — PACKAGE OUTLINE
PACKAGE OUTLINE
P5 · p05_fig01P5
SCH5127-NW (MQFP-128(14x20)) — Datasheet Page 5 (p05_fig01)
Datasheet Page 5 (p05_fig01)

Technical Specifications & Part Details (SCH5127-NW)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SCH5127-NW (MQFP-128(14x20)) is a 128-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.15 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, I2C, PWM, IrDA, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
14MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.15 mm (A1=0.10 mm)
Package family: TQFP (MQFP-128(14x20))
Pin Count & Lead PitchN / e
128 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, I2C, PWM, IrDA, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol128 auto-grouped pins
OK
IPC-7351B Land Pattern128 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (MQFP-128(14x20))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
20.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=0.50mm
Pad Size (W × L)Level B
0.25 × 1.50 mm
Pins / Total PadsTopology
128P / 128Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
MQFP-128(14x20)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SCH5127-NW (MQFP-128(14x20))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SCH5127-NW (MQFP-128(14x20))?

Manufactured by MICROCHIP, the SCH5127-NW is housed in a MQFP-128(14x20) package with 128 pins and a 0.50 mm lead pitch. Key pins include: 1 (V1_IN: Multiplexed I/O & Peripheral Pin V1_IN (General)), 2 (V2_IN: Multiplexed I/O & Peripheral Pin V2_IN (General)), 3 (VTRIP_IN: Multiplexed I/O & Peripheral Pin VTRIP_IN (General)), 4 (VTR: Multiplexed I/O & Peripheral Pin VTR (General)), 5 (nMTR0: Multiplexed I/O & Peripheral Pin nMTR0 (General)), 6 (nDSKCHG: Multiplexed I/O & Peripheral Pin nDSKCHG (General)).

What are the IPC-7351B PCB Footprint dimensions for SCH5127-NW?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SCH5127-NW (MQFP-128(14x20)) has a nominal body envelope of 14.00 × 20.00 mm, pitch e = 0.50 mm, and 128 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SCH5127-NW?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SCH5127-NW (MICROCHIP, MQFP-128(14x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (128 pins) & SCH5127 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1V1_INDigital_IOSignal terminal V1_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V1_IN. Supported peripheral buses: General.
2V2_INDigital_IOSignal terminal V2_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V2_IN. Supported peripheral buses: General.
3VTRIP_INDigital_IOSignal terminal VTRIP_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTRIP_IN. Supported peripheral buses: General.
4VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
5nMTR0Digital_IOSignal terminal nMTR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nMTR0. Supported peripheral buses: General.
6nDSKCHGDigital_IOSignal terminal nDSKCHG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDSKCHG. Supported peripheral buses: General.
7nDS0Digital_IOSignal terminal nDS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDS0. Supported peripheral buses: General.
8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9nDIRDigital_IOSignal terminal nDIR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDIR. Supported peripheral buses: General.
10nSTEPDigital_IOSignal terminal nSTEP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nSTEP. Supported peripheral buses: General.
11nWDATADigital_IOSignal terminal nWDATA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nWDATA. Supported peripheral buses: General.
12nWGATEDigital_IOSignal terminal nWGATE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nWGATE. Supported peripheral buses: General.
13nHDSELDigital_IOSignal terminal nHDSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nHDSEL. Supported peripheral buses: General.
14nINDEXDigital_IOSignal terminal nINDEX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nINDEX. Supported peripheral buses: General.
15nTRK0Digital_IOSignal terminal nTRK0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nTRK0. Supported peripheral buses: General.
16nWRTPRTDigital_IOSignal terminal nWRTPRT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nWRTPRT. Supported peripheral buses: General.
17nRDATADigital_IOSignal terminal nRDATA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRDATA. Supported peripheral buses: General.
18CLOCKIDigital_IOSignal terminal CLOCKI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLOCKI. Supported peripheral buses: General.
19LAD0Digital_IOSignal terminal LAD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD0. Supported peripheral buses: General.
20LAD1Digital_IOSignal terminal LAD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD1. Supported peripheral buses: General.
21LAD2Digital_IOSignal terminal LAD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD2. Supported peripheral buses: General.
22LAD3Digital_IOSignal terminal LAD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD3. Supported peripheral buses: General.
23nLFRAMEDigital_IOSignal terminal nLFRAME (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nLFRAME. Supported peripheral buses: General.
24nLDRQDigital_IOSignal terminal nLDRQ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nLDRQ. Supported peripheral buses: General.
25nPCI_RESETDigital_IOActive-low hardware reset terminal (nPCI_RESET): pulling this pin Low resets the processor core and peripherals.
26PCI_CLKDigital_IOSignal terminal PCI_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCI_CLK. Supported peripheral buses: General.
27SER_IRQDigital_IOSignal terminal SER_IRQ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SER_IRQ. Supported peripheral buses: General.
28nIDE_RSTDRV/GP10Digital_IOSignal terminal nIDE_RSTDRV/GP10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nIDE_RSTDRV/GP10. Supported peripheral buses: General.
29VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
30GP20/SPEAKER_OUTDigital_IOSignal terminal GP20/SPEAKER_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP20/SPEAKER_OUT. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
33nINTRD_INDigital_IOSignal terminal nINTRD_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nINTRD_IN. Supported peripheral buses: General.
34AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
35VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36GP27/nIO_SMI/P17Digital_IOSignal terminal GP27/nIO_SMI/P17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP27/nIO_SMI/P17. Supported peripheral buses: General.
37KDAT/GP21Digital_IOSignal terminal KDAT/GP21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: KDAT/GP21. Supported peripheral buses: General.
38KCLK/GP22Digital_IOSignal terminal KCLK/GP22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: KCLK/GP22. Supported peripheral buses: General.
39MDAT/GP32Digital_IOSignal terminal MDAT/GP32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDAT/GP32. Supported peripheral buses: General.
40MCLK/GP33Digital_IOSignal terminal MCLK/GP33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MCLK/GP33. Supported peripheral buses: General.
41GP36/nKBDRSTDigital_IOSignal terminal GP36/nKBDRST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP36/nKBDRST. Supported peripheral buses: General.
42GP37/A20MDigital_IOSignal terminal GP37/A20M (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP37/A20M. Supported peripheral buses: General.
43VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
44VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
45nINITDigital_IOSignal terminal nINIT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nINIT. Supported peripheral buses: General.
46nSLCTINDigital_IOSignal terminal nSLCTIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nSLCTIN. Supported peripheral buses: General.
47PD0Digital_IOSignal terminal PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
48PD1Digital_IOSignal terminal PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
49PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
50PD3Digital_IOSignal terminal PD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
51PD4Digital_IOSignal terminal PD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
52PD5Digital_IOSignal terminal PD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
53PD6Digital_IOSignal terminal PD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
54PD7Digital_IOSignal terminal PD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
55VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
56SLCTDigital_IOSignal terminal SLCT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLCT. Supported peripheral buses: General.
57PEDigital_IOSignal terminal PE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE. Supported peripheral buses: General.
58BUSYDigital_IOSignal terminal BUSY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BUSY. Supported peripheral buses: General.
59nACKDigital_IOSignal terminal nACK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nACK. Supported peripheral buses: General.
60nERRORDigital_IOSignal terminal nERROR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nERROR. Supported peripheral buses: General.
61nALFDigital_IOSignal terminal nALF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nALF. Supported peripheral buses: General.
62nSTROBEDigital_IOSignal terminal nSTROBE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nSTROBE. Supported peripheral buses: General.
63nRI1Digital_IOSignal terminal nRI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRI1. Supported peripheral buses: General.
64nDCD1Digital_IOSignal terminal nDCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDCD1. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload