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SCH3221-7U (WFBGA-64) — Symbol, Footprint IPC-7351B & 3D STEP Model

SCH3221-7U

MICROCHIPID: C633298WFBGA-64 · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SCH3221-7U (WFBGA-64)A2PCI RESET#_A3TEST VSS =A5GP41/nDCD4A7nRTS1/SYSOPTA9GP57/nDTR2A10GP56/nCTS2B1IO PME#_B2CLKI32B3GP11B4LDRQ#B5CLOCKIB7nCTS1B8nRI1B9GP52/RXD2/IRB10GP54/nDSR2B11GP55/nRTS2C1GP23/nLED2/IC2GP42/RXD4C10GP53/TXD2/IRC11GP50/nRI2D2LAD1D5VCCD6VSSD7VSSD10GP51/nDCD2E1LAD2E2LAD0E4VCCE8VCCE10nDTR1E11nDCD1F4VTRL10GP13/IRQIN1/L9GP43/TXD4L7GP37/nDTR3L5GP35/nRTS3L3GP32/RXD3L2GP31/nDCD3K11GP16K10GP22/IRMODE/K9GP20/IRRX2/IK8GP17K7GP47/nDTR4K5GP36/nCTS3K4GP33/TXD3K3GP30/nRI3K2SER_IRQK1PCI_CLKJ11GP12/IO SMI#J10GP21/IRTX2/WJ2CLKRUN#J1LPCPD#H10nDSR1H7VSSH6GP45/nRTS4H5VSSH2GP34/nDSR3G11RXD1G10TXD1G8GP46/nCTS4G4GP40/nRI4G2LFRAME#G1LAD3F8GP44/nDSR4Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
B1C1E1G1J1K1A2B2C2D2E2G2H2J2K2L2A3B3K3L3B4E4F4G4K4A5B5D5H5K5L5D6H6A7B7D7H7K7L7B8E8F8G8K8A9B9K9L9A10B10C10D10E10G10H10J10K10L10B11C11E11G11J11K11E=6.00mm · Pitch e=0.50mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2PCI RESET#_ISystem Enable & Hardware Reset (PCI RESET#_)
A3TEST VSS =GNDGround Reference Pin (TEST VSS =)
A5GP41/nDCD4I/OMultiplexed I/O & Peripheral Pin GP41/nDCD4 (General)
A7nRTS1/SYSOPTI/OMultiplexed I/O & Peripheral Pin nRTS1/SYSOPT (General)
A9GP57/nDTR2I/OMultiplexed I/O & Peripheral Pin GP57/nDTR2 (General)
A10GP56/nCTS2I/OMultiplexed I/O & Peripheral Pin GP56/nCTS2 (General)
B1IO PME#_I/OMultiplexed I/O & Peripheral Pin IO PME#_ (General)
B2CLKI32I/OMultiplexed I/O & Peripheral Pin CLKI32 (General)
B3GP11I/OMultiplexed I/O & Peripheral Pin GP11 (General)
B4LDRQ#I/OMultiplexed I/O & Peripheral Pin LDRQ# (General)
B5CLOCKII/OMultiplexed I/O & Peripheral Pin CLOCKI (General)
B7nCTS1I/OMultiplexed I/O & Peripheral Pin nCTS1 (General)
B8nRI1I/OMultiplexed I/O & Peripheral Pin nRI1 (General)
B9GP52/RXD2/IRRXI/OMultiplexed I/O & Peripheral Pin GP52/RXD2/IRRX (UART)
B10GP54/nDSR2I/OMultiplexed I/O & Peripheral Pin GP54/nDSR2 (General)
B11GP55/nRTS2I/OMultiplexed I/O & Peripheral Pin GP55/nRTS2 (General)
C1GP23/nLED2/IRQIN2I/OMultiplexed I/O & Peripheral Pin GP23/nLED2/IRQIN2 (General)
C2GP42/RXD4I/OMultiplexed I/O & Peripheral Pin GP42/RXD4 (UART)
C10GP53/TXD2/IRTXI/OMultiplexed I/O & Peripheral Pin GP53/TXD2/IRTX (UART)
C11GP50/nRI2I/OMultiplexed I/O & Peripheral Pin GP50/nRI2 (General)
D2LAD1I/OMultiplexed I/O & Peripheral Pin LAD1 (General)
D5VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
D6VSSGNDGround Reference Pin (VSS)
D7VSSGNDGround Reference Pin (VSS)
D10GP51/nDCD2I/OMultiplexed I/O & Peripheral Pin GP51/nDCD2 (General)
E1LAD2I/OMultiplexed I/O & Peripheral Pin LAD2 (General)
E2LAD0I/OMultiplexed I/O & Peripheral Pin LAD0 (General)
E4VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
E8VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
E10nDTR1I/OMultiplexed I/O & Peripheral Pin nDTR1 (General)
E11nDCD1I/OMultiplexed I/O & Peripheral Pin nDCD1 (General)
F4VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
F8GP44/nDSR4I/OMultiplexed I/O & Peripheral Pin GP44/nDSR4 (General)
G1LAD3I/OMultiplexed I/O & Peripheral Pin LAD3 (General)
G2LFRAME#I/OMultiplexed I/O & Peripheral Pin LFRAME# (General)
G4GP40/nRI4I/OMultiplexed I/O & Peripheral Pin GP40/nRI4 (General)
G8GP46/nCTS4I/OMultiplexed I/O & Peripheral Pin GP46/nCTS4 (General)
G10TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
G11RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
H2GP34/nDSR3I/OMultiplexed I/O & Peripheral Pin GP34/nDSR3 (General)
H5VSSGNDGround Reference Pin (VSS)
H6GP45/nRTS4I/OMultiplexed I/O & Peripheral Pin GP45/nRTS4 (General)
H7VSSGNDGround Reference Pin (VSS)
H10nDSR1I/OMultiplexed I/O & Peripheral Pin nDSR1 (General)
J1LPCPD#I/OMultiplexed I/O & Peripheral Pin LPCPD# (General)
J2CLKRUN#I/OMultiplexed I/O & Peripheral Pin CLKRUN# (General)
J10GP21/IRTX2/WDTI/OMultiplexed I/O & Peripheral Pin GP21/IRTX2/WDT (General)
J11GP12/IO SMI#_I/OMultiplexed I/O & Peripheral Pin GP12/IO SMI#_ (General)
K1PCI_CLKI/OMultiplexed I/O & Peripheral Pin PCI_CLK (General)
K2SER_IRQI/OMultiplexed I/O & Peripheral Pin SER_IRQ (General)
K3GP30/nRI3I/OMultiplexed I/O & Peripheral Pin GP30/nRI3 (General)
K4GP33/TXD3I/OMultiplexed I/O & Peripheral Pin GP33/TXD3 (UART)
K5GP36/nCTS3I/OMultiplexed I/O & Peripheral Pin GP36/nCTS3 (General)
K7GP47/nDTR4I/OMultiplexed I/O & Peripheral Pin GP47/nDTR4 (General)
K8GP17I/OMultiplexed I/O & Peripheral Pin GP17 (General)
K9GP20/IRRX2/IRQIN3I/OMultiplexed I/O & Peripheral Pin GP20/IRRX2/IRQIN3 (General)
K10GP22/IRMODE/IRRX3I/OMultiplexed I/O & Peripheral Pin GP22/IRMODE/IRRX3 (General)
K11GP16I/OMultiplexed I/O & Peripheral Pin GP16 (General)
L2GP31/nDCD3I/OMultiplexed I/O & Peripheral Pin GP31/nDCD3 (General)
L3GP32/RXD3I/OMultiplexed I/O & Peripheral Pin GP32/RXD3 (UART)
L5GP35/nRTS3I/OMultiplexed I/O & Peripheral Pin GP35/nRTS3 (General)
L7GP37/nDTR3I/OMultiplexed I/O & Peripheral Pin GP37/nDTR3 (General)
L9GP43/TXD4I/OMultiplexed I/O & Peripheral Pin GP43/TXD4 (UART)
L10GP13/IRQIN1/nLED1I/OMultiplexed I/O & Peripheral Pin GP13/IRQIN1/nLED1 (General)
PIN A2 PCI RESET#_
I
System Enable & Hardware Reset (PCI RESET#_)
Design note: PCI RESET#_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SCH3221-7U (MICROCHIP · WFBGA-64)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SCH3221-7U (WFBGA-64) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SCH3221-7U (WFBGA-64) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SCH3221-7U (WFBGA-64) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SCH3221-7U (WFBGA-64) - 4. Package Dimensions (D×E×A)
WFBGA-64 · 6.00×6.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
SCH3221-7U (WFBGA-64) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
SCH3221-7U (WFBGA-64) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for SCH3221
P117 · p117_fig01EXACT PACKAGE
SCH3221-7U (WFBGA-64) — FIGURE 12-1: 64-PIN WFBGA PACKAGE OUTLINE
FIGURE 12-1: 64-PIN WFBGA PACKAGE OUTLINE
P1 · p01_fig01377×200px
SCH3221-7U (WFBGA-64) — LPC I/O with Quad UARTs, GPIO and Wake
LPC I/O with Quad UARTs, GPIO and Wake
P7 · p07_fig011641×1599px
SCH3221-7U (WFBGA-64) — FIGURE 2-1: SCH3221 FOOTPRINT DIAGRAM, TOP VIEW
FIGURE 2-1: SCH3221 FOOTPRINT DIAGRAM, TOP VIEW
P7 · p07_fig01P7
SCH3221-7U (WFBGA-64) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P117 · p117_fig02139×351px
SCH3221-7U (WFBGA-64) — ;
;
P117 · p117_fig01P117
SCH3221-7U (WFBGA-64) — Datasheet Page 117 (p117_fig01)
Datasheet Page 117 (p117_fig01)

Technical Specifications & Part Details (SCH3221-7U)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SCH3221-7U (WFBGA-64) is a 64-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.35 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 70°C to 0°C with integrated IrDA, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
70°C to 0°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (WFBGA-64)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
IrDA, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — SCH3221 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WFBGA-64)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.50mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WFBGA-64
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SCH3221-7U (WFBGA-64)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SCH3221-7U (WFBGA-64)?

Manufactured by MICROCHIP, the SCH3221-7U is housed in a WFBGA-64 package with 64 pins and a 0.50 mm lead pitch. Key pins include: A2 (PCI RESET#_: System Enable & Hardware Reset (PCI RESET#_)), A3 (TEST VSS =: Ground Reference Pin (TEST VSS =)), A5 (GP41/nDCD4: Multiplexed I/O & Peripheral Pin GP41/nDCD4 (General)), A7 (nRTS1/SYSOPT: Multiplexed I/O & Peripheral Pin nRTS1/SYSOPT (General)), A9 (GP57/nDTR2: Multiplexed I/O & Peripheral Pin GP57/nDTR2 (General)), A10 (GP56/nCTS2: Multiplexed I/O & Peripheral Pin GP56/nCTS2 (General)).

What are the IPC-7351B PCB Footprint dimensions for SCH3221-7U?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SCH3221-7U (WFBGA-64) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SCH3221-7U?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SCH3221-7U (MICROCHIP, WFBGA-64) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & SCH3221 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2PCI RESET#_Digital_IOActive-low hardware reset terminal (PCI RESET#_): pulling this pin Low resets the processor core and peripherals.
A3TEST VSS =GND0V electrical ground return terminal (TEST VSS =) for internal core logic, I/O drivers, and analog sub-blocks.
A5GP41/nDCD4Digital_IOSignal terminal GP41/nDCD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP41/nDCD4. Supported peripheral buses: General.
A7nRTS1/SYSOPTDigital_IOSignal terminal nRTS1/SYSOPT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRTS1/SYSOPT. Supported peripheral buses: General.
A9GP57/nDTR2Digital_IOSignal terminal GP57/nDTR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP57/nDTR2. Supported peripheral buses: General.
A10GP56/nCTS2Digital_IOSignal terminal GP56/nCTS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP56/nCTS2. Supported peripheral buses: General.
B1IO PME#_Digital_IOSignal terminal IO PME#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO PME#_. Supported peripheral buses: General.
B2CLKI32Digital_IOSignal terminal CLKI32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKI32. Supported peripheral buses: General.
B3GP11Digital_IOSignal terminal GP11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP11. Supported peripheral buses: General.
B4LDRQ#Digital_IOSignal terminal LDRQ# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LDRQ#. Supported peripheral buses: General.
B5CLOCKIDigital_IOSignal terminal CLOCKI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLOCKI. Supported peripheral buses: General.
B7nCTS1Digital_IOSignal terminal nCTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nCTS1. Supported peripheral buses: General.
B8nRI1Digital_IOSignal terminal nRI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRI1. Supported peripheral buses: General.
B9GP52/RXD2/IRRXDigital_IOSignal terminal GP52/RXD2/IRRX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP52/RXD2/IRRX. Supported peripheral buses: UART.
B10GP54/nDSR2Digital_IOSignal terminal GP54/nDSR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP54/nDSR2. Supported peripheral buses: General.
B11GP55/nRTS2Digital_IOSignal terminal GP55/nRTS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP55/nRTS2. Supported peripheral buses: General.
C1GP23/nLED2/IRQIN2Digital_IOSignal terminal GP23/nLED2/IRQIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP23/nLED2/IRQIN2. Supported peripheral buses: General.
C2GP42/RXD4Digital_IOSignal terminal GP42/RXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP42/RXD4. Supported peripheral buses: UART.
C10GP53/TXD2/IRTXDigital_IOSignal terminal GP53/TXD2/IRTX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP53/TXD2/IRTX. Supported peripheral buses: UART.
C11GP50/nRI2Digital_IOSignal terminal GP50/nRI2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP50/nRI2. Supported peripheral buses: General.
D2LAD1Digital_IOSignal terminal LAD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD1. Supported peripheral buses: General.
D5VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D10GP51/nDCD2Digital_IOSignal terminal GP51/nDCD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP51/nDCD2. Supported peripheral buses: General.
E1LAD2Digital_IOSignal terminal LAD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD2. Supported peripheral buses: General.
E2LAD0Digital_IOSignal terminal LAD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD0. Supported peripheral buses: General.
E4VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E8VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E10nDTR1Digital_IOSignal terminal nDTR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDTR1. Supported peripheral buses: General.
E11nDCD1Digital_IOSignal terminal nDCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDCD1. Supported peripheral buses: General.
F4VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
F8GP44/nDSR4Digital_IOSignal terminal GP44/nDSR4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP44/nDSR4. Supported peripheral buses: General.
G1LAD3Digital_IOSignal terminal LAD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD3. Supported peripheral buses: General.
G2LFRAME#Digital_IOSignal terminal LFRAME# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LFRAME#. Supported peripheral buses: General.
G4GP40/nRI4Digital_IOSignal terminal GP40/nRI4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP40/nRI4. Supported peripheral buses: General.
G8GP46/nCTS4Digital_IOSignal terminal GP46/nCTS4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP46/nCTS4. Supported peripheral buses: General.
G10TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
G11RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
H2GP34/nDSR3Digital_IOSignal terminal GP34/nDSR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP34/nDSR3. Supported peripheral buses: General.
H5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
H6GP45/nRTS4Digital_IOSignal terminal GP45/nRTS4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP45/nRTS4. Supported peripheral buses: General.
H7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
H10nDSR1Digital_IOSignal terminal nDSR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nDSR1. Supported peripheral buses: General.
J1LPCPD#Digital_IOSignal terminal LPCPD# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LPCPD#. Supported peripheral buses: General.
J2CLKRUN#Digital_IOSignal terminal CLKRUN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKRUN#. Supported peripheral buses: General.
J10GP21/IRTX2/WDTDigital_IOSignal terminal GP21/IRTX2/WDT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP21/IRTX2/WDT. Supported peripheral buses: General.
J11GP12/IO SMI#_Digital_IOSignal terminal GP12/IO SMI#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP12/IO SMI#_. Supported peripheral buses: General.
K1PCI_CLKDigital_IOSignal terminal PCI_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCI_CLK. Supported peripheral buses: General.
K2SER_IRQDigital_IOSignal terminal SER_IRQ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SER_IRQ. Supported peripheral buses: General.
K3GP30/nRI3Digital_IOSignal terminal GP30/nRI3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP30/nRI3. Supported peripheral buses: General.
K4GP33/TXD3Digital_IOSignal terminal GP33/TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP33/TXD3. Supported peripheral buses: UART.
K5GP36/nCTS3Digital_IOSignal terminal GP36/nCTS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP36/nCTS3. Supported peripheral buses: General.
K7GP47/nDTR4Digital_IOSignal terminal GP47/nDTR4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP47/nDTR4. Supported peripheral buses: General.
K8GP17Digital_IOSignal terminal GP17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP17. Supported peripheral buses: General.
K9GP20/IRRX2/IRQIN3Digital_IOSignal terminal GP20/IRRX2/IRQIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP20/IRRX2/IRQIN3. Supported peripheral buses: General.
K10GP22/IRMODE/IRRX3Digital_IOSignal terminal GP22/IRMODE/IRRX3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP22/IRMODE/IRRX3. Supported peripheral buses: General.
K11GP16Digital_IOSignal terminal GP16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP16. Supported peripheral buses: General.
L2GP31/nDCD3Digital_IOSignal terminal GP31/nDCD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP31/nDCD3. Supported peripheral buses: General.
L3GP32/RXD3Digital_IOSignal terminal GP32/RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP32/RXD3. Supported peripheral buses: UART.
L5GP35/nRTS3Digital_IOSignal terminal GP35/nRTS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP35/nRTS3. Supported peripheral buses: General.
L7GP37/nDTR3Digital_IOSignal terminal GP37/nDTR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP37/nDTR3. Supported peripheral buses: General.
L9GP43/TXD4Digital_IOSignal terminal GP43/TXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP43/TXD4. Supported peripheral buses: UART.
L10GP13/IRQIN1/nLED1Digital_IOSignal terminal GP13/IRQIN1/nLED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP13/IRQIN1/nLED1. Supported peripheral buses: General.
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