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KSZ8061RNBW-TR (QFN-32-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

KSZ8061RNBW-TR

MICROCHIPID: C631642QFN-32-EP(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · KSZ8061RNBW-TR (QFN-32-EP(5x5))1XI2XO3AVDDH4TXP5TXM6RXP7RXM8AVDDL9VDDL10MDIO11MDC12RXER/QWF13RXDV/ CONFIG14RXD3/ PHYAD015VDDIO16RXD2/ PHYAD117RXD1/ PHYAD233EP32SIGDET31REXT30VDDL29INTRP/ NAND 28RESET#27CRS/ CONFIG126TXD325TXD224LED023TXD122TXD021TXEN20TXC19RXC/ CONFIG018RXD0/ AUTONEGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
2XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
3AVDDHPowerPower Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)
4TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
5TXMI/OMultiplexed I/O & Peripheral Pin TXM (General)
6RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
7RXMI/OMultiplexed I/O & Peripheral Pin RXM (General)
8AVDDLPowerPower Supply Input (AVDDL — 3.3V / 5.0V Standard Logic)
9VDDLPowerPower Supply Input (VDDL — 3.3V / 5.0V Standard Logic)
10MDIOI/OMultiplexed I/O & Peripheral Pin MDIO (General)
11MDCI/OMultiplexed I/O & Peripheral Pin MDC (General)
12RXER/QWFI/OMultiplexed I/O & Peripheral Pin RXER/QWF (General)
13RXDV/ CONFIG2I/OMultiplexed I/O & Peripheral Pin RXDV/ CONFIG2 (UART)
14RXD3/ PHYAD0I/OMultiplexed I/O & Peripheral Pin RXD3/ PHYAD0 (UART)
15VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
16RXD2/ PHYAD1I/OMultiplexed I/O & Peripheral Pin RXD2/ PHYAD1 (UART)
17RXD1/ PHYAD2I/OMultiplexed I/O & Peripheral Pin RXD1/ PHYAD2 (UART)
18RXD0/ AUTONEGI/OMultiplexed I/O & Peripheral Pin RXD0/ AUTONEG (UART)
19RXC/ CONFIG0I/OMultiplexed I/O & Peripheral Pin RXC/ CONFIG0 (General)
20TXCI/OMultiplexed I/O & Peripheral Pin TXC (General)
21TXENI/OMultiplexed I/O & Peripheral Pin TXEN (General)
22TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
23TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
24LED0I/OMultiplexed I/O & Peripheral Pin LED0 (General)
25TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
26TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
27CRS/ CONFIG1I/OMultiplexed I/O & Peripheral Pin CRS/ CONFIG1 (General)
28RESET#ISystem Enable & Hardware Reset (RESET#)
29INTRP/ NAND Tree#_I/OMultiplexed I/O & Peripheral Pin INTRP/ NAND Tree#_ (General)
30VDDLPowerPower Supply Input (VDDL — 3.3V / 5.0V Standard Logic)
31REXTI/OMultiplexed I/O & Peripheral Pin REXT (General)
32SIGDETI/OMultiplexed I/O & Peripheral Pin SIGDET (General)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 XI
I/O
Multiplexed I/O & Peripheral Pin XI (RTC/CLK)
Design note: Crystal/Oscillator/ExternalClockInput 25MHz±50ppm ThisinputreferencestheAVDDHpowersupply . .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: KSZ8061RNBW-TR (MICROCHIP · QFN-32-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
KSZ8061RNBW-TR (QFN-32-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
KSZ8061RNBW-TR (QFN-32-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
KSZ8061RNBW-TR (QFN-32-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
KSZ8061RNBW-TR (QFN-32-EP(5x5)) - 4. Package Dimensions (D×E×A)
QFN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
KSZ8061RNBW-TR (QFN-32-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
KSZ8061RNBW-TR (QFN-32-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for KSZ8061
P1 · p01_fig01376×200px
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — 10BASE-T/100BASE-TX Physical Layer Transceiver
10BASE-T/100BASE-TX Physical Layer Transceiver
P5 · p05_fig01914×953px
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — FIGURE 2-1: 32-QFN OR WQFN KSZ8061MNX PIN ASSIGNMENT (TOP VIEW)
FIGURE 2-1: 32-QFN OR WQFN KSZ8061MNX PIN ASSIGNMENT (TOP VIEW)
P29 · p29_fig011421×781px
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — FIGURE 3-9: KSZ8061MNX POWER AND GROUND CONNECTIONS
FIGURE 3-9: KSZ8061MNX POWER AND GROUND CONNECTIONS
P29 · p29_fig021379×828px
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — FIGURE 3-10: KSZ8061MNG POWER AND GROUND CONNECTIONS
FIGURE 3-10: KSZ8061MNG POWER AND GROUND CONNECTIONS
P29 · p29_fig02P29
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — Datasheet Page 29 (p29_fig02)
Datasheet Page 29 (p29_fig02)
P58 · p58_fig011585×1726px
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — FIGURE 11-1: 32-LEAD WQFN 5 MM X 5 MM PACKAGE
FIGURE 11-1: 32-LEAD WQFN 5 MM X 5 MM PACKAGE
P58 · p58_fig01P58
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — Datasheet Page 58 (p58_fig01)
Datasheet Page 58 (p58_fig01)
P59 · p59_fig012147×2339px
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — FIGURE 11-2: 32-LEAD QFN 5 MM X 5 MM PACKAGE
FIGURE 11-2: 32-LEAD QFN 5 MM X 5 MM PACKAGE
P59 · p59_fig01P59
KSZ8061RNBW-TR (QFN-32-EP(5x5)) — Datasheet Page 59 (p59_fig01)
Datasheet Page 59 (p59_fig01)

Technical Specifications & Part Details (KSZ8061RNBW-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:KSZ8061RNBW-TR (QFN-32-EP(5x5)) is a 32-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.10×3.10mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32-EP(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — KSZ8061RNBW-TR (QFN-32-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of KSZ8061RNBW-TR (QFN-32-EP(5x5))?

Manufactured by MICROCHIP, the KSZ8061RNBW-TR is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 2 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)), 3 (AVDDH: Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)), 4 (TXP: Multiplexed I/O & Peripheral Pin TXP (General)), 5 (TXM: Multiplexed I/O & Peripheral Pin TXM (General)), 6 (RXP: Multiplexed I/O & Peripheral Pin RXP (General)).

What are the IPC-7351B PCB Footprint dimensions for KSZ8061RNBW-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KSZ8061RNBW-TR (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.10 × 3.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KSZ8061RNBW-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KSZ8061RNBW-TR (MICROCHIP, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & KSZ8061 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
2XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
3AVDDHPower_InPrimary positive power supply input (AVDDH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4TXPDigital_IOSignal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
5TXMDigital_IOSignal terminal TXM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXM. Supported peripheral buses: General.
6RXPDigital_IOSignal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
7RXMDigital_IOSignal terminal RXM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXM. Supported peripheral buses: General.
8AVDDLPower_InPrimary positive power supply input (AVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9VDDLPower_InPrimary positive power supply input (VDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10MDIOOpen_DrainSignal terminal MDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIO. Supported peripheral buses: General.
11MDCDigital_IOSignal terminal MDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDC. Supported peripheral buses: General.
12RXER/QWFDigital_IOSignal terminal RXER/QWF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXER/QWF. Supported peripheral buses: General.
13RXDV/ CONFIG2Digital_IOSignal terminal RXDV/ CONFIG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXDV/ CONFIG2. Supported peripheral buses: UART.
14RXD3/ PHYAD0Digital_IOSignal terminal RXD3/ PHYAD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3/ PHYAD0. Supported peripheral buses: UART.
15VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16RXD2/ PHYAD1Digital_IOSignal terminal RXD2/ PHYAD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2/ PHYAD1. Supported peripheral buses: UART.
17RXD1/ PHYAD2Digital_IOSignal terminal RXD1/ PHYAD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1/ PHYAD2. Supported peripheral buses: UART.
18RXD0/ AUTONEGDigital_IOSignal terminal RXD0/ AUTONEG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0/ AUTONEG. Supported peripheral buses: UART.
19RXC/ CONFIG0Digital_IOSignal terminal RXC/ CONFIG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXC/ CONFIG0. Supported peripheral buses: General.
20TXCDigital_IOSignal terminal TXC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXC. Supported peripheral buses: General.
21TXENDigital_IOSignal terminal TXEN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXEN. Supported peripheral buses: General.
22TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
23TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
24LED0Digital_IOSignal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General.
25TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
26TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
27CRS/ CONFIG1Digital_IOSignal terminal CRS/ CONFIG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CRS/ CONFIG1. Supported peripheral buses: General.
28RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
29INTRP/ NAND Tree#_Open_DrainSignal terminal INTRP/ NAND Tree#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INTRP/ NAND Tree#_. Supported peripheral buses: General.
30VDDLPower_InPrimary positive power supply input (VDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31REXTDigital_IOSignal terminal REXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REXT. Supported peripheral buses: General.
32SIGDETDigital_IOSignal terminal SIGDET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SIGDET. Supported peripheral buses: General.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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