PIC16F818T-I/ML (QFN-28-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC16F818T-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC16F818T-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (RA3/AN3/VREF+/C1IN+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+/C1IN+ (General)), 3 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)), 4 (RA5/AN4/SS/C2OUT: Multiplexed I/O & Peripheral Pin RA5/AN4/SS/C2OUT (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA7/OSC1/CLKIN: Multiplexed I/O & Peripheral Pin RA7/OSC1/CLKIN (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC16F818T-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F818T-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.10 × 4.10 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F818T-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F818T-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	IO1	I/O	General Purpose Digital I/O Pin IO1
2	RA3/AN3/VREF+/C1IN+	Analog	Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+/C1IN+ (General)
3	RA4/T0CKI/C1OUT	I/O	Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)
4	RA5/AN4/SS/C2OUT	I/O	Multiplexed I/O & Peripheral Pin RA5/AN4/SS/C2OUT (General)
5	VSS	GND	Ground Reference Pin (VSS)
6	RA7/OSC1/CLKIN	I/O	Multiplexed I/O & Peripheral Pin RA7/OSC1/CLKIN (RTC/CLK)
7	RA6/OSC2/CLKOUT	I/O	Multiplexed I/O & Peripheral Pin RA6/OSC2/CLKOUT (RTC/CLK)
8	RC0/T1OSO/T1CKI	I/O	Multiplexed I/O & Peripheral Pin RC0/T1OSO/T1CKI (General)
9	RC1/T1OSI/CCP2	I/O	Multiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2 (General)
10	RC2/P1A/CCP1	I/O	Multiplexed I/O & Peripheral Pin RC2/P1A/CCP1 (General)
11	RC3/SCK/SCL	I/O	Multiplexed I/O & Peripheral Pin RC3/SCK/SCL (SPI, I2C)
12	RC4/SDI/SDA	I/O	Multiplexed I/O & Peripheral Pin RC4/SDI/SDA (I2C)
13	RC5/SDO	I/O	Multiplexed I/O & Peripheral Pin RC5/SDO (General)
14	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
15	RC7/RX/DT	I/O	Multiplexed I/O & Peripheral Pin RC7/RX/DT (General)
16	VSS	GND	Ground Reference Pin (VSS)
17	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
18	RB0/AN12/INT	I/O	Multiplexed I/O & Peripheral Pin RB0/AN12/INT (General)
19	RB1/AN10/P1C/C12IN3-	I/O	Multiplexed I/O & Peripheral Pin RB1/AN10/P1C/C12IN3- (General)
20	RB2/AN8/P1B	I/O	Multiplexed I/O & Peripheral Pin RB2/AN8/P1B (General)
21	RB3/AN9/PGM/C12IN2-	I/O	Multiplexed I/O & Peripheral Pin RB3/AN9/PGM/C12IN2- (General)
22	RB4/AN11/P1D	I/O	Multiplexed I/O & Peripheral Pin RB4/AN11/P1D (General)
23	RB5/AN13/T1G#	I/O	Multiplexed I/O & Peripheral Pin RB5/AN13/T1G# (General)
24	RB6/ICSPCLK	I/O	Multiplexed I/O & Peripheral Pin RB6/ICSPCLK (General)
25	RB7/ICSPDAT	I/O	Multiplexed I/O & Peripheral Pin RB7/ICSPDAT (General)
26	RE3/MCLR#/VPP	I/O	Multiplexed I/O & Peripheral Pin RE3/MCLR#/VPP (General)
27	RA0/AN0/ULPWU/C12IN0-	I/O	Multiplexed I/O & Peripheral Pin RA0/AN0/ULPWU/C12IN0- (General)
28	RA1/AN1/C12IN1-	I/O	Multiplexed I/O & Peripheral Pin RA1/AN1/C12IN1- (General)
29	PAD	I/O	Multiplexed I/O & Peripheral Pin PAD (General)

PIN 1 IO1

I/O

General Purpose Digital I/O Pin IO1

Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC16F818T-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC16F818T-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC16F818T-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC16F818T-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC16F818T-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC16F818T-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)

Showing 1–12 of 17 uncropped original figures for PIC16F818T / PIC16F818

P1 · p01_fig011777×735px

250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz

P1 · p01_fig021780×468px

PIC16F818T-I/ML (QFN-28-EP(6x6)) —  2001-2013 Microchip Technology Inc. DS39598F-page 1 | Device | Program Memory Data Memory | I/O Pins 10-bit A/D (ch) | CCP (PWM) | SSP | Timers 8/16-bit Flash (Bytes) | # Single-Word | Instructions | SRAM (Bytes) | EEPROM | (Bytes) SPI Sl

P1 · p01_fig01P1

Datasheet Page 1 (p01_fig01)

P2 · p02_fig01719×712px

28-Pin QFN(1)

P2 · p02_fig02846×447px

RA3/AN3/VREF+

P2 · p02_fig031096×944px

Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.

P2 · p02_fig03P2

Datasheet Page 2 (p02_fig03)

P5 · p05_fig011777×425px

PIC16F818T-I/ML (QFN-28-EP(6x6)) — PIC16F818/819 | 1.0 DEVICE OVERVIEW | There are 16 I/O pins that are user configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: | PIC16F819 2K x14 256 x 8 256 x 8 | Device Progra

PIC16F818/819 | 1.0 DEVICE OVERVIEW | There are 16 I/O pins that are user configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: | PIC16F819 2K x14 256 x 8 256 x 8 | Device Progra

P5 · p05_fig02868×339px

PIC16F818T-I/ML (QFN-28-EP(6x6)) — TABLE 1-1: AVAILABLE MEMORY IN PIC16F818/819 DEVICES | Device Program | Flash | Data Memory | Data EEPROM | PIC16F818 1K x 14 128 x 8 128 x 8

P5 · p05_fig01P5

Datasheet Page 5 (p05_fig01)

P66 · p66_fig011754×691px

Capture Enable

P66 · p66_fig021753×640px

FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (PIC16F818T-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC16F818T-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 0.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.0V to 5.5V supply operation across -10°C to +85°C with integrated SPI, I2C, ADC, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.0V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-10°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 0.85 mm (A1=0.03 mm)

Package family: QFN (QFN-28-EP(6x6))

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI, I2C, ADC, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 4.10×4.10mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — PIC16F818T / PIC16F818 (2)

Select package variant or sibling MPN sharing this datasheet

SSOP-20 · 20P

PIC16F818-I/SS

MICROCHIP·SSOP-20

IPC-7351B

20P6.5×4.4×1.10mmP=0.65mm

PIC16F818T / PIC16F818 (SSOP-20)

QFN-28-EP(6x6) · 29P

PIC16F818T-I/ML

MICROCHIP·QFN-28-EP(6x6)

IPC-7351B

29P6.0×6.0×0.85mmP=0.65mm

PIC16F818T / PIC16F818 (QFN-28-EP(6x6))

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-28-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F818T-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F818T-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC16F818T-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (RA3/AN3/VREF+/C1IN+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+/C1IN+ (General)), 3 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)), 4 (RA5/AN4/SS/C2OUT: Multiplexed I/O & Peripheral Pin RA5/AN4/SS/C2OUT (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA7/OSC1/CLKIN: Multiplexed I/O & Peripheral Pin RA7/OSC1/CLKIN (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F818T-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F818T-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.10 × 4.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F818T-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F818T-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC16F818T / PIC16F818 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	IO1	Digital_IO	General Purpose Digital I/O Pin IO1
2	RA3/AN3/VREF+/C1IN+	Analog	Signal terminal RA3/AN3/VREF+/C1IN+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+/C1IN+. Supported peripheral buses: General.
3	RA4/T0CKI/C1OUT	Digital_IO	Signal terminal RA4/T0CKI/C1OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI/C1OUT. Supported peripheral buses: General.
4	RA5/AN4/SS/C2OUT	Digital_IO	Signal terminal RA5/AN4/SS/C2OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA5/AN4/SS/C2OUT. Supported peripheral buses: General.
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	RA7/OSC1/CLKIN	Digital_IO	Signal terminal RA7/OSC1/CLKIN (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA7/OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
7	RA6/OSC2/CLKOUT	Digital_IO	Signal terminal RA6/OSC2/CLKOUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA6/OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
8	RC0/T1OSO/T1CKI	Digital_IO	Signal terminal RC0/T1OSO/T1CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T1CKI. Supported peripheral buses: General.
9	RC1/T1OSI/CCP2	Digital_IO	Signal terminal RC1/T1OSI/CCP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2. Supported peripheral buses: General.
10	RC2/P1A/CCP1	Digital_IO	Signal terminal RC2/P1A/CCP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/P1A/CCP1. Supported peripheral buses: General.
11	RC3/SCK/SCL	Digital_IO	Signal terminal RC3/SCK/SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC3/SCK/SCL. Supported peripheral buses: SPI, I2C.
12	RC4/SDI/SDA	Digital_IO	Signal terminal RC4/SDI/SDA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/SDI/SDA. Supported peripheral buses: I2C.
13	RC5/SDO	Digital_IO	Signal terminal RC5/SDO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/SDO. Supported peripheral buses: General.
14	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
15	RC7/RX/DT	Digital_IO	Signal terminal RC7/RX/DT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
16	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
18	RB0/AN12/INT	Digital_IO	Signal terminal RB0/AN12/INT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/AN12/INT. Supported peripheral buses: General.
19	RB1/AN10/P1C/C12IN3-	Digital_IO	Signal terminal RB1/AN10/P1C/C12IN3- (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/AN10/P1C/C12IN3-. Supported peripheral buses: General.
20	RB2/AN8/P1B	Digital_IO	Signal terminal RB2/AN8/P1B (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/AN8/P1B. Supported peripheral buses: General.
21	RB3/AN9/PGM/C12IN2-	Digital_IO	Signal terminal RB3/AN9/PGM/C12IN2- (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/AN9/PGM/C12IN2-. Supported peripheral buses: General.
22	RB4/AN11/P1D	Digital_IO	Signal terminal RB4/AN11/P1D (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/AN11/P1D. Supported peripheral buses: General.
23	RB5/AN13/T1G#	Digital_IO	Signal terminal RB5/AN13/T1G# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/AN13/T1G#. Supported peripheral buses: General.
24	RB6/ICSPCLK	Digital_IO	Signal terminal RB6/ICSPCLK (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/ICSPCLK. Supported peripheral buses: General.
25	RB7/ICSPDAT	Digital_IO	Signal terminal RB7/ICSPDAT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/ICSPDAT. Supported peripheral buses: General.
26	RE3/MCLR#/VPP	Digital_IO	Signal terminal RE3/MCLR#/VPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE3/MCLR#/VPP. Supported peripheral buses: General.
27	RA0/AN0/ULPWU/C12IN0-	Digital_IO	Signal terminal RA0/AN0/ULPWU/C12IN0- (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0/ULPWU/C12IN0-. Supported peripheral buses: General.
28	RA1/AN1/C12IN1-	Digital_IO	Signal terminal RA1/AN1/C12IN1- (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1/C12IN1-. Supported peripheral buses: General.
29	PAD	Digital_IO	Signal terminal PAD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: PAD. Supported peripheral buses: General.

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