dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7))?

Manufactured by MICROCHIP, the dsPIC33EP32GS505T-I/PT is housed in a TQFP-48-EP(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (TMS/ASDA1/RP41/RB9(4): Multiplexed I/O & Peripheral Pin TMS/ASDA1/RP41/RB9(4) (General)), 2 (RP54/RC6: Multiplexed I/O & Peripheral Pin RP54/RC6 (General)), 3 (RP55/RC7: Multiplexed I/O & Peripheral Pin RP55/RC7 (General)), 4 (RP56/RC8: Multiplexed I/O & Peripheral Pin RP56/RC8 (General)), 5 (RP57/RC9: Multiplexed I/O & Peripheral Pin RP57/RC9 (General)), 6 (VSS: Ground Reference Pin (VSS)).

Q: What are the IPC-7351B PCB Footprint dimensions for dsPIC33EP32GS505T-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33EP32GS505T-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33EP32GS505T-I/PT (MICROCHIP, TQFP-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	TMS/ASDA1/RP41/RB9(4)	I/O	Multiplexed I/O & Peripheral Pin TMS/ASDA1/RP41/RB9(4) (General)
2	RP54/RC6	I/O	Multiplexed I/O & Peripheral Pin RP54/RC6 (General)
3	RP55/RC7	I/O	Multiplexed I/O & Peripheral Pin RP55/RC7 (General)
4	RP56/RC8	I/O	Multiplexed I/O & Peripheral Pin RP56/RC8 (General)
5	RP57/RC9	I/O	Multiplexed I/O & Peripheral Pin RP57/RC9 (General)
6	VSS	GND	Ground Reference Pin (VSS)
7	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
8	N/C	I/O	Multiplexed I/O & Peripheral Pin N/C (General)
9	RP42/PWM3H/RB10	I/O	Multiplexed I/O & Peripheral Pin RP42/PWM3H/RB10 (PWM)
10	RP43/PWM3L/RB11	I/O	Multiplexed I/O & Peripheral Pin RP43/PWM3L/RB11 (PWM)
11	RPI44/PWM2H/RB12	I/O	Multiplexed I/O & Peripheral Pin RPI44/PWM2H/RB12 (PWM)
12	RPI45/PWM2L/CTPLS/RB13	I/O	Multiplexed I/O & Peripheral Pin RPI45/PWM2L/CTPLS/RB13 (PWM)
13	TDO/RA10	I/O	Multiplexed I/O & Peripheral Pin TDO/RA10 (General)
14	TDI/RA7	I/O	Multiplexed I/O & Peripheral Pin TDI/RA7 (General)
15	RPI46/PWM1H/T3CK/RB14	I/O	Multiplexed I/O & Peripheral Pin RPI46/PWM1H/T3CK/RB14 (PWM)
16	RPI47/PWM1L/T5CK/RB15	I/O	Multiplexed I/O & Peripheral Pin RPI47/PWM1L/T5CK/RB15 (PWM)
17	AVSS	GND	Ground Reference Pin (AVSS)
18	AVDD	Power	Power Supply Input (AVDD — 3.0V to 3.6V)
19	MCLR#	I/O	Multiplexed I/O & Peripheral Pin MCLR# (General)
20	N/C	I/O	Multiplexed I/O & Peripheral Pin N/C (General)
21	AN0/OA2OUT/RA0	I/O	Multiplexed I/O & Peripheral Pin AN0/OA2OUT/RA0 (General)
22	AN1/C2IN1+/RA1	I/O	Multiplexed I/O & Peripheral Pin AN1/C2IN1+/RA1 (General)
23	IO12	I/O	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	IO13	I/O	GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25	IO14	I/O	GPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26	IO21	I/O	GPIO21 / RTC_GPIO21
27	IO47	I/O	GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28	AN7/C3IN1-/C4IN1-/RC1	I/O	Multiplexed I/O & Peripheral Pin AN7/C3IN1-/C4IN1-/RC1 (General)
29	IO29	I/O	General Purpose Digital I/O Pin IO29
30	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
31	VSS	GND	Ground Reference Pin (VSS)
32	N/C	I/O	Multiplexed I/O & Peripheral Pin N/C (General)
33	OSC1/CLKI/RA2	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA2 (RTC/CLK)
34	OSC2/CLKO/RA3	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO/RA3 (RTC/CLK)
35	SDA2/RPI24/RA8	I/O	Multiplexed I/O & Peripheral Pin SDA2/RPI24/RA8 (I2C)
36	FLT32/SCL2/RP36/RB4	I/O	Multiplexed I/O & Peripheral Pin FLT32/SCL2/RP36/RB4 (I2C)
37	IO37	I/O	General Purpose Digital I/O Pin IO37
38	SDI1/RPI25/RA9	I/O	Multiplexed I/O & Peripheral Pin SDI1/RPI25/RA9 (General)
39	SCK1/RPI51/RC3	I/O	Multiplexed I/O & Peripheral Pin SCK1/RPI51/RC3 (SPI)
40	SDA1/RPI52/RC4	I/O	Multiplexed I/O & Peripheral Pin SDA1/RPI52/RC4 (I2C)
41	SCL1/RPI53/RC5	I/O	Multiplexed I/O & Peripheral Pin SCL1/RPI53/RC5 (I2C)
42	VSS	GND	Ground Reference Pin (VSS)
43	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
44	N/C	I/O	Multiplexed I/O & Peripheral Pin N/C (General)
45	PGED2/ASDA2/RP37/RB5	I/O	Multiplexed I/O & Peripheral Pin PGED2/ASDA2/RP37/RB5 (General)
46	PGEC2/ASCL2/RP38/RB6	I/O	Multiplexed I/O & Peripheral Pin PGEC2/ASCL2/RP38/RB6 (General)
47	RP39/INT0/RB7	I/O	Multiplexed I/O & Peripheral Pin RP39/INT0/RB7 (General)
48	IO48	I/O	General Purpose Digital I/O Pin IO48

PIN 1 TMS/ASDA1/RP41/RB9(4)

I/O

Multiplexed I/O & Peripheral Pin TMS/ASDA1/RP41/RB9(4) (General)

Design note: Signal terminal TMS/ASDA1/RP41/RB9(4) (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TMS/ASDA1/RP41/RB9(4). Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) - 2. Standard Pinout (Top View)

True package pinout (48 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) - 4. Package Dimensions (D×E×A)

TQFP-48-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) - 5. Recommended Land Pattern

IPC-7351B Footprint (48 Pads)Expand ›

6. Application SchematicSCHEMATIC

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for DSPIC33EP32G

P1 · p01_fig01377×200px

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) — 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators

16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators

P11 · p11_fig011580×1319px

FIGURE 1-1: dsPIC33EPXXGS50X FAMILY BLOCK DIAGRAM

P18 · p18_fig011456×1006px

FIGURE 2-4: INTERLEAVED PFC

P77 · p77_fig011777×969px

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

P126 · p126_fig01874×366px

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) — MOV 0xFF00, W0 ; Configure PORTB<15:8> ; as inputs MOV W0, TRISB ; and PORTB<7:0> ; as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction

MOV 0xFF00, W0 ; Configure PORTB<15:8> ; as inputs MOV W0, TRISB ; and PORTB<7:0> ; as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction

P128 · p128_fig01867×999px

FIGURE 10-2: REMAPPABLE INPUT FOR U1RX

P128 · p128_fig01P128

Datasheet Page 128 (p128_fig01)

P285 · p285_fig01867×874px

FIGURE 23-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3)

P285 · p285_fig01P285

Datasheet Page 285 (p285_fig01)

P360 · p360_fig011784×2735px

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) — dsPIC33EPXXGS50X FAMILY | DS70005127D-page 360  2013-2017 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch |

P369 · p369_fig011779×2735px

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) —  2013-2017 Microchip Technology Inc. DS70005127D-page 369 | dsPIC33EPXXGS50X FAMILY | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch |

P371 · p371_fig011779×2735px

dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) — dsPIC33EPXXGS50X FAMILY - 48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP] - http:/www.microchip.com/packaging |  2013-2017 Microchip Technology Inc. DS70005127D-page 371 | dsPIC33EPXXGS50X FAMILY | Microchip Technology Drawing C04

dsPIC33EPXXGS50X FAMILY - 48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP] - http:/www.microchip.com/packaging |  2013-2017 Microchip Technology Inc. DS70005127D-page 371 | dsPIC33EPXXGS50X FAMILY | Microchip Technology Drawing C04

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (dsPIC33EP32GS505T-I/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +85°C with integrated UART, SPI, I2C, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

40 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

7.00 × 7.00 × 1.20 mm (A1=0.10 mm)

Package family: TQFP (TQFP-48-EP(7x7))

Pin Count & Lead PitchN / e

48 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol48 auto-grouped pins

IPC-7351B Land Pattern48 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-48-EP(7x7))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

7.00 × 7.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.20mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.50 mm

Pins / Total PadsTopology

48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TQFP-48-EP(7x7)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7))?

Manufactured by MICROCHIP, the dsPIC33EP32GS505T-I/PT is housed in a TQFP-48-EP(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (TMS/ASDA1/RP41/RB9(4): Multiplexed I/O & Peripheral Pin TMS/ASDA1/RP41/RB9(4) (General)), 2 (RP54/RC6: Multiplexed I/O & Peripheral Pin RP54/RC6 (General)), 3 (RP55/RC7: Multiplexed I/O & Peripheral Pin RP55/RC7 (General)), 4 (RP56/RC8: Multiplexed I/O & Peripheral Pin RP56/RC8 (General)), 5 (RP57/RC9: Multiplexed I/O & Peripheral Pin RP57/RC9 (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for dsPIC33EP32GS505T-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33EP32GS505T-I/PT (TQFP-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33EP32GS505T-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33EP32GS505T-I/PT (MICROCHIP, TQFP-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & DSPIC33EP32G Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	TMS/ASDA1/RP41/RB9(4)	Digital_IO	Signal terminal TMS/ASDA1/RP41/RB9(4) (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TMS/ASDA1/RP41/RB9(4). Supported peripheral buses: General.
2	RP54/RC6	Digital_IO	Signal terminal RP54/RC6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP54/RC6. Supported peripheral buses: General.
3	RP55/RC7	Digital_IO	Signal terminal RP55/RC7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP55/RC7. Supported peripheral buses: General.
4	RP56/RC8	Digital_IO	Signal terminal RP56/RC8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP56/RC8. Supported peripheral buses: General.
5	RP57/RC9	Digital_IO	Signal terminal RP57/RC9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP57/RC9. Supported peripheral buses: General.
6	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7	VCAP	Digital_IO	Signal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
8	N/C	Digital_IO	Signal terminal N/C (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
9	RP42/PWM3H/RB10	Digital_IO	Signal terminal RP42/PWM3H/RB10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP42/PWM3H/RB10. Supported peripheral buses: PWM.
10	RP43/PWM3L/RB11	Digital_IO	Signal terminal RP43/PWM3L/RB11 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP43/PWM3L/RB11. Supported peripheral buses: PWM.
11	RPI44/PWM2H/RB12	Digital_IO	Signal terminal RPI44/PWM2H/RB12 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI44/PWM2H/RB12. Supported peripheral buses: PWM.
12	RPI45/PWM2L/CTPLS/RB13	Digital_IO	Signal terminal RPI45/PWM2L/CTPLS/RB13 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI45/PWM2L/CTPLS/RB13. Supported peripheral buses: PWM.
13	TDO/RA10	Digital_IO	Signal terminal TDO/RA10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDO/RA10. Supported peripheral buses: General.
14	TDI/RA7	Digital_IO	Signal terminal TDI/RA7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDI/RA7. Supported peripheral buses: General.
15	RPI46/PWM1H/T3CK/RB14	Digital_IO	Signal terminal RPI46/PWM1H/T3CK/RB14 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI46/PWM1H/T3CK/RB14. Supported peripheral buses: PWM.
16	RPI47/PWM1L/T5CK/RB15	Digital_IO	Signal terminal RPI47/PWM1L/T5CK/RB15 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI47/PWM1L/T5CK/RB15. Supported peripheral buses: PWM.
17	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
18	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
19	MCLR#	Digital_IO	Signal terminal MCLR# (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
20	N/C	Digital_IO	Signal terminal N/C (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
21	AN0/OA2OUT/RA0	Digital_IO	Signal terminal AN0/OA2OUT/RA0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN0/OA2OUT/RA0. Supported peripheral buses: General.
22	AN1/C2IN1+/RA1	Digital_IO	Signal terminal AN1/C2IN1+/RA1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN1/C2IN1+/RA1. Supported peripheral buses: General.
23	IO12	Digital_IO	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	IO13	Digital_IO	GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25	IO14	Digital_IO	GPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26	IO21	Digital_IO	GPIO21 / RTC_GPIO21
27	IO47	Digital_IO	GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28	AN7/C3IN1-/C4IN1-/RC1	Digital_IO	Signal terminal AN7/C3IN1-/C4IN1-/RC1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN7/C3IN1-/C4IN1-/RC1. Supported peripheral buses: General.
29	IO29	Digital_IO	General Purpose Digital I/O Pin IO29
30	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	N/C	Digital_IO	Signal terminal N/C (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
33	OSC1/CLKI/RA2	Digital_IO	Signal terminal OSC1/CLKI/RA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/RA2. Supported peripheral buses: RTC/CLK.
34	OSC2/CLKO/RA3	Digital_IO	Signal terminal OSC2/CLKO/RA3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC2/CLKO/RA3. Supported peripheral buses: RTC/CLK.
35	SDA2/RPI24/RA8	Digital_IO	Signal terminal SDA2/RPI24/RA8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SDA2/RPI24/RA8. Supported peripheral buses: I2C.
36	FLT32/SCL2/RP36/RB4	Digital_IO	Signal terminal FLT32/SCL2/RP36/RB4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: FLT32/SCL2/RP36/RB4. Supported peripheral buses: I2C.
37	IO37	Digital_IO	General Purpose Digital I/O Pin IO37
38	SDI1/RPI25/RA9	Digital_IO	Signal terminal SDI1/RPI25/RA9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SDI1/RPI25/RA9. Supported peripheral buses: General.
39	SCK1/RPI51/RC3	Digital_IO	Signal terminal SCK1/RPI51/RC3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SCK1/RPI51/RC3. Supported peripheral buses: SPI.
40	SDA1/RPI52/RC4	Digital_IO	Signal terminal SDA1/RPI52/RC4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SDA1/RPI52/RC4. Supported peripheral buses: I2C.
41	SCL1/RPI53/RC5	Digital_IO	Signal terminal SCL1/RPI53/RC5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SCL1/RPI53/RC5. Supported peripheral buses: I2C.
42	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
43	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
44	N/C	Digital_IO	Signal terminal N/C (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
45	PGED2/ASDA2/RP37/RB5	Digital_IO	Signal terminal PGED2/ASDA2/RP37/RB5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PGED2/ASDA2/RP37/RB5. Supported peripheral buses: General.
46	PGEC2/ASCL2/RP38/RB6	Digital_IO	Signal terminal PGEC2/ASCL2/RP38/RB6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PGEC2/ASCL2/RP38/RB6. Supported peripheral buses: General.
47	RP39/INT0/RB7	Digital_IO	Signal terminal RP39/INT0/RB7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP39/INT0/RB7. Supported peripheral buses: General.
48	IO48	Digital_IO	General Purpose Digital I/O Pin IO48

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