USB7051T-I/KDX (VQFN-100-EP(12x12)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of USB7051T-I/KDX (VQFN-100-EP(12x12))?

Manufactured by MICROCHIP, the USB7051T-I/KDX is housed in a VQFN-100-EP(12x12) package with 101 pins and a 0.40 mm lead pitch. Key pins include: 1 (RESET_N: System Enable & Hardware Reset (RESET_N)), 2 (PF30: Multiplexed I/O & Peripheral Pin PF30 (General)), 3 (PF31: Multiplexed I/O & Peripheral Pin PF31 (General)), 4 (DP1_VBUS_MON: Power Supply Input (DP1_VBUS_MON — 3.3V / 5.0V Standard Logic)), 5 (USB2DN_DP1: Multiplexed I/O & Peripheral Pin USB2DN_DP1 (USB)), 6 (USB2DN_DM1: Multiplexed I/O & Peripheral Pin USB2DN_DM1 (USB)).

Q: What are the IPC-7351B PCB Footprint dimensions for USB7051T-I/KDX?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), USB7051T-I/KDX (VQFN-100-EP(12x12)) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.40 mm, and 101 copper pads plus a central exposed thermal pad (EPAD) of 8.10 × 8.10 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for USB7051T-I/KDX?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for USB7051T-I/KDX (MICROCHIP, VQFN-100-EP(12x12)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 12.00mm × 12.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (101/101)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RESET_N	I	System Enable & Hardware Reset (RESET_N)
2	PF30	I/O	Multiplexed I/O & Peripheral Pin PF30 (General)
3	PF31	I/O	Multiplexed I/O & Peripheral Pin PF31 (General)
4	DP1_VBUS_MON	Power	Power Supply Input (DP1_VBUS_MON — 3.3V / 5.0V Standard Logic)
5	USB2DN_DP1	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DP1 (USB)
6	USB2DN_DM1	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DM1 (USB)
7	USB3DN_TXDP1A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDP1A (USB, UART)
8	USB3DN_TXDM1A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDM1A (USB, UART)
9	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
10	USB3DN_RXDP1A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDP1A (USB, UART)
11	USB3DN_RXDM1A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDM1A (USB, UART)
12	DP1_CC1	I/O	Multiplexed I/O & Peripheral Pin DP1_CC1 (General)
13	DP1_CC2	I/O	Multiplexed I/O & Peripheral Pin DP1_CC2 (General)
14	USB2DN_DP4	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DP4 (USB)
15	USB2DN_DM4	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DM4 (USB)
16	USB3DN_TXDP1B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDP1B (USB, UART)
17	USB3DN_TXDM1B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDM1B (USB, UART)
18	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
19	USB3DN_RXDP1B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDP1B (USB, UART)
20	USB3DN_RXDM1B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDM1B (USB, UART)
21	CFG_STRAP1#	I/O	Multiplexed I/O & Peripheral Pin CFG_STRAP1# (General)
22	CFG_STRAP2#	I/O	Multiplexed I/O & Peripheral Pin CFG_STRAP2# (General)
23	CFG_STRAP3#	I/O	Multiplexed I/O & Peripheral Pin CFG_STRAP3# (General)
24	TESTEN	I	Input-Only Pin TESTEN (General)
25	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
26	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
27	DP2_CC1	I/O	Multiplexed I/O & Peripheral Pin DP2_CC1 (General)
28	DP2_CC2	I/O	Multiplexed I/O & Peripheral Pin DP2_CC2 (General)
29	USB2DN_DP2	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DP2 (USB)
30	USB2DN_DM2	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DM2 (USB)
31	USB3DN_TXDP2A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDP2A (USB, UART)
32	USB3DN_TXDM2A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDM2A (USB, UART)
33	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
34	USB3DN_RXDP2A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDP2A (USB, UART)
35	USB3DN_RXDM2A	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDM2A (USB, UART)
36	DP2_VBUS_MON	Power	Power Supply Input (DP2_VBUS_MON — 3.3V / 5.0V Standard Logic)
37	USB3DN_TXDP2B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDP2B (USB, UART)
38	USB3DN_TXDM2B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDM2B (USB, UART)
39	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
40	USB3DN_RXDP2B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDP2B (USB, UART)
41	USB3DN_RXDM2B	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDM2B (USB, UART)
42	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
43	PF2	I/O	Multiplexed I/O & Peripheral Pin PF2 (General)
44	PF3	I/O	Multiplexed I/O & Peripheral Pin PF3 (General)
45	PF4	I/O	Multiplexed I/O & Peripheral Pin PF4 (General)
46	PF5	I/O	Multiplexed I/O & Peripheral Pin PF5 (General)
47	PF6	I/O	Multiplexed I/O & Peripheral Pin PF6 (General)
48	PF7	I/O	Multiplexed I/O & Peripheral Pin PF7 (General)
49	PF8	I/O	Multiplexed I/O & Peripheral Pin PF8 (General)
50	PF9	I/O	Multiplexed I/O & Peripheral Pin PF9 (General)
51	PF10	I/O	Multiplexed I/O & Peripheral Pin PF10 (General)
52	PF11	I/O	Multiplexed I/O & Peripheral Pin PF11 (General)
53	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
54	PF12	I/O	Multiplexed I/O & Peripheral Pin PF12 (General)
55	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
56	PF13	I/O	Multiplexed I/O & Peripheral Pin PF13 (General)
57	PF14	I/O	Multiplexed I/O & Peripheral Pin PF14 (General)
58	PF15	I/O	Multiplexed I/O & Peripheral Pin PF15 (General)
59	PF16	I/O	Multiplexed I/O & Peripheral Pin PF16 (General)
60	PF17	I/O	Multiplexed I/O & Peripheral Pin PF17 (General)
61	PF18	I/O	Multiplexed I/O & Peripheral Pin PF18 (General)
62	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
63	TEST1	I/O	Multiplexed I/O & Peripheral Pin TEST1 (General)
64	TEST2	I/O	Multiplexed I/O & Peripheral Pin TEST2 (General)
65	TEST3	I/O	Multiplexed I/O & Peripheral Pin TEST3 (General)
66	PF19	I/O	Multiplexed I/O & Peripheral Pin PF19 (General)
67	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
68	SPI_CLK/PF21	I/O	Multiplexed I/O & Peripheral Pin SPI_CLK/PF21 (SPI)
69	IO69	I/O	General Purpose Digital I/O Pin IO69
70	SPI_D0/CFG_BC_EN#/PF22	I/O	Multiplexed I/O & Peripheral Pin SPI_D0/CFG_BC_EN#/PF22 (SPI)
71	SPI_D1/PF23	I/O	Multiplexed I/O & Peripheral Pin SPI_D1/PF23 (SPI)
72	SPI_D2/PF24	I/O	Multiplexed I/O & Peripheral Pin SPI_D2/PF24 (SPI)
73	SPI_D3/PF25	I/O	Multiplexed I/O & Peripheral Pin SPI_D3/PF25 (SPI)
74	PF29	I/O	Multiplexed I/O & Peripheral Pin PF29 (General)
75	PF26	I/O	Multiplexed I/O & Peripheral Pin PF26 (General)
76	PF27	I/O	Multiplexed I/O & Peripheral Pin PF27 (General)
77	PF28	I/O	Multiplexed I/O & Peripheral Pin PF28 (General)
78	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
79	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
80	VBUS_MON_UP	Power	Power Supply Input (VBUS_MON_UP — 3.3V / 5.0V Standard Logic)
81	USB2DN_DP3	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DP3 (USB)
82	USB2DN_DM3	I/O	Multiplexed I/O & Peripheral Pin USB2DN_DM3 (USB)
83	USB3DN_TXDP3	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDP3 (USB, UART)
84	USB3DN_TXDM3	I/O	Multiplexed I/O & Peripheral Pin USB3DN_TXDM3 (USB, UART)
85	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
86	USB3DN_RXDP3	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDP3 (USB, UART)
87	USB3DN_RXDM3	I/O	Multiplexed I/O & Peripheral Pin USB3DN_RXDM3 (USB, UART)
88	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
89	USB2UP_DP	I/O	Multiplexed I/O & Peripheral Pin USB2UP_DP (USB)
90	USB2UP_DM	I/O	Multiplexed I/O & Peripheral Pin USB2UP_DM (USB)
91	USB3UP_TXDP	I/O	Multiplexed I/O & Peripheral Pin USB3UP_TXDP (USB, UART)
92	USB3UP_TXDM	I/O	Multiplexed I/O & Peripheral Pin USB3UP_TXDM (USB, UART)
93	VCORE	I/O	Multiplexed I/O & Peripheral Pin VCORE (General)
94	USB3UP_RXDP	I/O	Multiplexed I/O & Peripheral Pin USB3UP_RXDP (USB, UART)
95	USB3UP_RXDM	I/O	Multiplexed I/O & Peripheral Pin USB3UP_RXDM (USB, UART)
96	ATEST	I/O	Multiplexed I/O & Peripheral Pin ATEST (General)
97	XTALO	I/O	Multiplexed I/O & Peripheral Pin XTALO (RTC/CLK)
98	XTALI/CLK_IN	I/O	Multiplexed I/O & Peripheral Pin XTALI/CLK_IN (RTC/CLK)
99	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
100	RBIAS	I/O	Multiplexed I/O & Peripheral Pin RBIAS (General)
101	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 RESET_N

System Enable & Hardware Reset (RESET_N)

Design note: Active-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

USB7051T-I/KDX (VQFN-100-EP(12x12)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

USB7051T-I/KDX (VQFN-100-EP(12x12)) - 2. Standard Pinout (Top View)

True package pinout (101 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

USB7051T-I/KDX (VQFN-100-EP(12x12)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

USB7051T-I/KDX (VQFN-100-EP(12x12)) - 4. Package Dimensions (D×E×A)

VQFN-100-EP(12x12) · 12.00×12.00mm · Pitch 0.40mmExpand ›

5. Recommended Land PatternLAND PATTERN

USB7051T-I/KDX (VQFN-100-EP(12x12)) - 5. Recommended Land Pattern

IPC-7351B Footprint (101 Pads)Expand ›

6. Application SchematicSCHEMATIC

USB7051T-I/KDX (VQFN-100-EP(12x12)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)

Showing 1–7 of 7 uncropped original figures for USB7051

P1 · p01_fig01377×200px

4-Port USB 3.2 Gen 1 PD SmartHub™ IC

P8 · p08_fig011784×1924px

FIGURE 3-1: USB7051 100-VQFN PIN ASSIGNMENTS

P8 · p08_fig01P8

Datasheet Page 8 (p08_fig01)

P49 · p49_fig011781×2202px

FIGURE 10-1: 100-VQFN PACKAGE (DRAWING)

P49 · p49_fig01P49

Datasheet Page 49 (p49_fig01)

P51 · p51_fig011232×1408px

FIGURE 10-3: 100-VQFN PACKAGE (LAND-PATTERN)

P51 · p51_fig01P51

Datasheet Page 51 (p51_fig01)

Technical Specifications & Part Details (USB7051T-I/KDX)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:USB7051T-I/KDX (VQFN-100-EP(12x12)) is a 100-pin standard electronic & interconnect component featuring a 12.00 × 12.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

25 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

12.00 × 12.00 × 0.90 mm (A1=0.03 mm)

Package family: QFN (VQFN-100-EP(12x12))

Pin Count & Lead PitchN / e

100 Pins | Pitch e = 0.40 mm (15.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol101 auto-grouped pins

IPC-7351B Land Pattern101 pads · Pitch 0.40mm

IPC-7525 60% Solder PasteEPAD 8.10×8.10mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VQFN-100-EP(12x12))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

12.00 × 12.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.90mm · e=0.40mm

Pad Size (W × L)Level B

0.20 × 1.05 mm

Pins / Total PadsTopology

101P / 101Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit VQFN-100-EP(12x12)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — USB7051T-I/KDX (VQFN-100-EP(12x12))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of USB7051T-I/KDX (VQFN-100-EP(12x12))?

Manufactured by MICROCHIP, the USB7051T-I/KDX is housed in a VQFN-100-EP(12x12) package with 101 pins and a 0.40 mm lead pitch. Key pins include: 1 (RESET_N: System Enable & Hardware Reset (RESET_N)), 2 (PF30: Multiplexed I/O & Peripheral Pin PF30 (General)), 3 (PF31: Multiplexed I/O & Peripheral Pin PF31 (General)), 4 (DP1_VBUS_MON: Power Supply Input (DP1_VBUS_MON — 3.3V / 5.0V Standard Logic)), 5 (USB2DN_DP1: Multiplexed I/O & Peripheral Pin USB2DN_DP1 (USB)), 6 (USB2DN_DM1: Multiplexed I/O & Peripheral Pin USB2DN_DM1 (USB)).

What are the IPC-7351B PCB Footprint dimensions for USB7051T-I/KDX?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), USB7051T-I/KDX (VQFN-100-EP(12x12)) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.40 mm, and 101 copper pads plus a central exposed thermal pad (EPAD) of 8.10 × 8.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for USB7051T-I/KDX?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for USB7051T-I/KDX (MICROCHIP, VQFN-100-EP(12x12)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (101 pins) & USB7051 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RESET_N	Digital_IO	Active-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals.
2	PF30	Digital_IO	Signal terminal PF30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF30. Supported peripheral buses: General.
3	PF31	Digital_IO	Signal terminal PF31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF31. Supported peripheral buses: General.
4	DP1_VBUS_MON	Power_In	Primary positive power supply input (DP1_VBUS_MON) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5	USB2DN_DP1	Digital_IO	Signal terminal USB2DN_DP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2DN_DP1. Supported peripheral buses: USB.
6	USB2DN_DM1	Digital_IO	Signal terminal USB2DN_DM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2DN_DM1. Supported peripheral buses: USB.
7	USB3DN_TXDP1A	Digital_IO	Signal terminal USB3DN_TXDP1A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDP1A. Supported peripheral buses: USB, UART.
8	USB3DN_TXDM1A	Digital_IO	Signal terminal USB3DN_TXDM1A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDM1A. Supported peripheral buses: USB, UART.
9	VCORE	Digital_IO	Signal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
10	USB3DN_RXDP1A	Digital_IO	Signal terminal USB3DN_RXDP1A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDP1A. Supported peripheral buses: USB, UART.
11	USB3DN_RXDM1A	Digital_IO	Signal terminal USB3DN_RXDM1A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDM1A. Supported peripheral buses: USB, UART.
12	DP1_CC1	Digital_IO	Signal terminal DP1_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP1_CC1. Supported peripheral buses: General.
13	DP1_CC2	Digital_IO	Signal terminal DP1_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP1_CC2. Supported peripheral buses: General.
14	USB2DN_DP4	Digital_IO	Signal terminal USB2DN_DP4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2DN_DP4. Supported peripheral buses: USB.
15	USB2DN_DM4	Digital_IO	Signal terminal USB2DN_DM4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2DN_DM4. Supported peripheral buses: USB.
16	USB3DN_TXDP1B	Digital_IO	Signal terminal USB3DN_TXDP1B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDP1B. Supported peripheral buses: USB, UART.
17	USB3DN_TXDM1B	Digital_IO	Signal terminal USB3DN_TXDM1B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDM1B. Supported peripheral buses: USB, UART.
18	VCORE	Digital_IO	Signal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
19	USB3DN_RXDP1B	Digital_IO	Signal terminal USB3DN_RXDP1B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDP1B. Supported peripheral buses: USB, UART.
20	USB3DN_RXDM1B	Digital_IO	Signal terminal USB3DN_RXDM1B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDM1B. Supported peripheral buses: USB, UART.
21	CFG_STRAP1#	Digital_IO	Signal terminal CFG_STRAP1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG_STRAP1#. Supported peripheral buses: General.
22	CFG_STRAP2#	Digital_IO	Signal terminal CFG_STRAP2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG_STRAP2#. Supported peripheral buses: General.
23	CFG_STRAP3#	Digital_IO	Signal terminal CFG_STRAP3# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG_STRAP3#. Supported peripheral buses: General.
24	TESTEN	Digital_IO	Signal terminal TESTEN (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TESTEN. Supported peripheral buses: General.
25	VCORE	Digital_IO	Signal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
26	VDD33	Power_In	Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
27	DP2_CC1	Digital_IO	Signal terminal DP2_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP2_CC1. Supported peripheral buses: General.
28	DP2_CC2	Digital_IO	Signal terminal DP2_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP2_CC2. Supported peripheral buses: General.
29	USB2DN_DP2	Digital_IO	Signal terminal USB2DN_DP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2DN_DP2. Supported peripheral buses: USB.
30	USB2DN_DM2	Digital_IO	Signal terminal USB2DN_DM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2DN_DM2. Supported peripheral buses: USB.
31	USB3DN_TXDP2A	Digital_IO	Signal terminal USB3DN_TXDP2A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDP2A. Supported peripheral buses: USB, UART.
32	USB3DN_TXDM2A	Digital_IO	Signal terminal USB3DN_TXDM2A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDM2A. Supported peripheral buses: USB, UART.
33	VCORE	Digital_IO	Signal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
34	USB3DN_RXDP2A	Digital_IO	Signal terminal USB3DN_RXDP2A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDP2A. Supported peripheral buses: USB, UART.
35	USB3DN_RXDM2A	Digital_IO	Signal terminal USB3DN_RXDM2A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDM2A. Supported peripheral buses: USB, UART.
36	DP2_VBUS_MON	Power_In	Primary positive power supply input (DP2_VBUS_MON) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37	USB3DN_TXDP2B	Digital_IO	Signal terminal USB3DN_TXDP2B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDP2B. Supported peripheral buses: USB, UART.
38	USB3DN_TXDM2B	Digital_IO	Signal terminal USB3DN_TXDM2B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_TXDM2B. Supported peripheral buses: USB, UART.
39	VCORE	Digital_IO	Signal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
40	USB3DN_RXDP2B	Digital_IO	Signal terminal USB3DN_RXDP2B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDP2B. Supported peripheral buses: USB, UART.
41	USB3DN_RXDM2B	Digital_IO	Signal terminal USB3DN_RXDM2B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3DN_RXDM2B. Supported peripheral buses: USB, UART.
42	VDD33	Power_In	Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43	PF2	Digital_IO	Signal terminal PF2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
44	PF3	Digital_IO	Signal terminal PF3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
45	PF4	Digital_IO	Signal terminal PF4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
46	PF5	Digital_IO	Signal terminal PF5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
47	PF6	Digital_IO	Signal terminal PF6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF6. Supported peripheral buses: General.
48	PF7	Digital_IO	Signal terminal PF7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF7. Supported peripheral buses: General.
49	PF8	Digital_IO	Signal terminal PF8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF8. Supported peripheral buses: General.
50	PF9	Digital_IO	Signal terminal PF9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF9. Supported peripheral buses: General.
51	PF10	Digital_IO	Signal terminal PF10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General.
52	PF11	Digital_IO	Signal terminal PF11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF11. Supported peripheral buses: General.
53	VDD33	Power_In	Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
54	PF12	Digital_IO	Signal terminal PF12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General.
55	VCORE	Digital_IO	Signal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
56	PF13	Digital_IO	Signal terminal PF13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General.
57	PF14	Digital_IO	Signal terminal PF14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General.
58	PF15	Digital_IO	Signal terminal PF15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF15. Supported peripheral buses: General.
59	PF16	Digital_IO	Signal terminal PF16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF16. Supported peripheral buses: General.
60	PF17	Digital_IO	Signal terminal PF17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF17. Supported peripheral buses: General.
61	PF18	Digital_IO	Signal terminal PF18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF18. Supported peripheral buses: General.
62	VDD33	Power_In	Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
63	TEST1	Digital_IO	Signal terminal TEST1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST1. Supported peripheral buses: General.
64	TEST2	Digital_IO	Signal terminal TEST2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST2. Supported peripheral buses: General.

4D Studio: USB7051T-I/KDX Permalink: /part/C628637 MICROCHIP VQFN-100-EP(12x12)All Packages All Manufacturers