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SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

SST39VF800A-70-4I-MAQE-T

MICROCHIPID: C628439WFBGA-48(4x6) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6))A2VSSA3CE#A4A0A5A1A6A2B1DQ0B2OE#B3DQ8B4A5B5A3B6A4C1DQ1C2DQ9C3DQ10C4A18C5A7C6A6D1DQ2D2NCD5NCD6A17E1DQ3E6NCF1VDDL5A14L4A15L3A16L2DQ7L1VSSK6A11K5A13K4A12K3DQ11K2DQ6K1DQ15J6A9J5A10J4A8J3DQ4J2DQ5J1DQ14H6NCH5NCH2NCH1DQ13G6WE#G1DQ12F6NCGrid Pitch = 2.54mm (IEEE-315)-20.3-15.2-10.2-5.105.110.215.220.335.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
L5L4L3L2L1K6K5K4K3K2K1J6J5J4J3J2J1H6H5H2H1G6G1F6F1E6E1D6D5D2D1C6C5C4C3C2C1B6B5B4B3B2B1A6A5A4A3A2E=6.00mm · Pitch e=0.50mmD=4.00mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 6.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2VSSGNDGround Reference Pin (VSS)
A3CE#I/OMultiplexed I/O & Peripheral Pin CE# (General)
A4A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
A5A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
A6A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
B1DQ0I/OMultiplexed I/O & Peripheral Pin DQ0 (General)
B2OE#I/OMultiplexed I/O & Peripheral Pin OE# (General)
B3DQ8I/OMultiplexed I/O & Peripheral Pin DQ8 (General)
B4A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
B5A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
B6A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
C1DQ1I/OMultiplexed I/O & Peripheral Pin DQ1 (General)
C2DQ9I/OMultiplexed I/O & Peripheral Pin DQ9 (General)
C3DQ10I/OMultiplexed I/O & Peripheral Pin DQ10 (General)
C4A18I/OMultiplexed I/O & Peripheral Pin A18 (General)
C5A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
C6A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
D1DQ2I/OMultiplexed I/O & Peripheral Pin DQ2 (General)
D2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
D5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
D6A17I/OMultiplexed I/O & Peripheral Pin A17 (General)
E1DQ3I/OMultiplexed I/O & Peripheral Pin DQ3 (General)
E6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
F1VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
F6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
G1DQ12I/OMultiplexed I/O & Peripheral Pin DQ12 (General)
G6WE#I/OMultiplexed I/O & Peripheral Pin WE# (General)
H1DQ13I/OMultiplexed I/O & Peripheral Pin DQ13 (General)
H2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
H5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
H6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
J1DQ14I/OMultiplexed I/O & Peripheral Pin DQ14 (General)
J2DQ5I/OMultiplexed I/O & Peripheral Pin DQ5 (General)
J3DQ4I/OMultiplexed I/O & Peripheral Pin DQ4 (General)
J4A8I/OMultiplexed I/O & Peripheral Pin A8 (General)
J5A10I/OMultiplexed I/O & Peripheral Pin A10 (General)
J6A9I/OMultiplexed I/O & Peripheral Pin A9 (General)
K1DQ15I/OMultiplexed I/O & Peripheral Pin DQ15 (General)
K2DQ6I/OMultiplexed I/O & Peripheral Pin DQ6 (General)
K3DQ11I/OMultiplexed I/O & Peripheral Pin DQ11 (General)
K4A12I/OMultiplexed I/O & Peripheral Pin A12 (General)
K5A13I/OMultiplexed I/O & Peripheral Pin A13 (General)
K6A11I/OMultiplexed I/O & Peripheral Pin A11 (General)
L1VSSGNDGround Reference Pin (VSS)
L2DQ7I/OMultiplexed I/O & Peripheral Pin DQ7 (General)
L3A16I/OMultiplexed I/O & Peripheral Pin A16 (General)
L4A15I/OMultiplexed I/O & Peripheral Pin A15 (General)
L5A14I/OMultiplexed I/O & Peripheral Pin A14 (General)
PIN A2 VSS
GND
Ground Reference Pin (VSS)
Design note: 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SST39VF800A-70-4I-MAQE-T (MICROCHIP · WFBGA-48(4x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) - 4. Package Dimensions (D×E×A)
WFBGA-48(4x6) · 6.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for SST39VF200A / SST39VF800A
P1 · p01_fig01469×310px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — A Microchip Technology Company | 2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company | 2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A
P1 · p01_fig01P1
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig01468×310px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Product Description
Product Description
P3 · p03_fig01468×310px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Block Diagram
Block Diagram
P3 · p03_fig022037×1080px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Figure 1: Functional Block Diagram
Figure 1: Functional Block Diagram
P3 · p03_fig031972×1115px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Figure 1: Functional Block Diagram
Figure 1: Functional Block Diagram
P6 · p06_fig01468×310px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Table 1: Pin Description
Table 1: Pin Description
P31 · p31_fig01468×310px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Packaging Diagrams
Packaging Diagrams
P31 · p31_fig022037×1954px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Figure 22:48-Lead Thin Small Outline Package (TSOP) 12mm x 20mm
Figure 22:48-Lead Thin Small Outline Package (TSOP) 12mm x 20mm
P34 · p34_fig01468×310px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — A Microchip Technology Company svete, ® A Microchip Technology Company
A Microchip Technology Company svete, ® A Microchip Technology Company
P34 · p34_fig022037×1412px
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Figure 25:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm
Figure 25:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm
P34 · p34_fig02P34
SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) — Datasheet Page 34 (p34_fig02)
Datasheet Page 34 (p34_fig02)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (SST39VF800A-70-4I-MAQE-T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) is a 48-pin standard electronic & interconnect component featuring a 4.00 × 6.00 × 1.35 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
14 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 6.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (WFBGA-48(4x6))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WFBGA-48(4x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.50mm
Pad Size (W × L)Level B
0.26 × 0.26 mm
Pins / Total PadsTopology
48P / 48Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WFBGA-48(4x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6))?

Manufactured by MICROCHIP, the SST39VF800A-70-4I-MAQE-T is housed in a WFBGA-48(4x6) package with 48 pins and a 0.50 mm lead pitch. Key pins include: A2 (VSS: Ground Reference Pin (VSS)), A3 (CE#: Multiplexed I/O & Peripheral Pin CE# (General)), A4 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), A5 (A1: Multiplexed I/O & Peripheral Pin A1 (General)), A6 (A2: Multiplexed I/O & Peripheral Pin A2 (General)), B1 (DQ0: Multiplexed I/O & Peripheral Pin DQ0 (General)).

What are the IPC-7351B PCB Footprint dimensions for SST39VF800A-70-4I-MAQE-T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SST39VF800A-70-4I-MAQE-T (WFBGA-48(4x6)) has a nominal body envelope of 6.00 × 4.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SST39VF800A-70-4I-MAQE-T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SST39VF800A-70-4I-MAQE-T (MICROCHIP, WFBGA-48(4x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & SST39VF200A / SST39VF800A Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A3CE#Digital_IOSignal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
A4A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
A5A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
A6A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
B1DQ0Digital_IOSignal terminal DQ0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ0. Supported peripheral buses: General.
B2OE#Digital_IOSignal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.
B3DQ8Digital_IOSignal terminal DQ8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ8. Supported peripheral buses: General.
B4A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
B5A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
B6A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
C1DQ1Digital_IOSignal terminal DQ1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ1. Supported peripheral buses: General.
C2DQ9Digital_IOSignal terminal DQ9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ9. Supported peripheral buses: General.
C3DQ10Digital_IOSignal terminal DQ10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ10. Supported peripheral buses: General.
C4A18Digital_IOSignal terminal A18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A18. Supported peripheral buses: General.
C5A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
C6A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
D1DQ2Digital_IOSignal terminal DQ2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ2. Supported peripheral buses: General.
D2NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
D5NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
D6A17Digital_IOSignal terminal A17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A17. Supported peripheral buses: General.
E1DQ3Digital_IOSignal terminal DQ3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ3. Supported peripheral buses: General.
E6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
F1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
G1DQ12Digital_IOSignal terminal DQ12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ12. Supported peripheral buses: General.
G6WE#Digital_IOSignal terminal WE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WE#. Supported peripheral buses: General.
H1DQ13Digital_IOSignal terminal DQ13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ13. Supported peripheral buses: General.
H2NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
H5NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
H6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
J1DQ14Digital_IOSignal terminal DQ14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ14. Supported peripheral buses: General.
J2DQ5Digital_IOSignal terminal DQ5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ5. Supported peripheral buses: General.
J3DQ4Digital_IOSignal terminal DQ4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ4. Supported peripheral buses: General.
J4A8Digital_IOSignal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
J5A10Digital_IOSignal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
J6A9Digital_IOSignal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
K1DQ15Digital_IOSignal terminal DQ15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ15. Supported peripheral buses: General.
K2DQ6Digital_IOSignal terminal DQ6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ6. Supported peripheral buses: General.
K3DQ11Digital_IOSignal terminal DQ11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ11. Supported peripheral buses: General.
K4A12Digital_IOSignal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
K5A13Digital_IOSignal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
K6A11Digital_IOSignal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
L1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
L2DQ7Digital_IOSignal terminal DQ7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ7. Supported peripheral buses: General.
L3A16Digital_IOSignal terminal A16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A16. Supported peripheral buses: General.
L4A15Digital_IOSignal terminal A15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A15. Supported peripheral buses: General.
L5A14Digital_IOSignal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
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