MIC4129YME-TR (SOIC-8-EP) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MIC4129YME-TR (SOIC-8-EP)?

Manufactured by MICROCHIP, the MIC4129YME-TR is housed in a SOIC-8-EP package with 9 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 4.5V to 20V. Key pins include: 1 (VS: Multiplexed I/O & Peripheral Pin VS (General)), 2 (IN: Multiplexed I/O & Peripheral Pin IN (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (GND: Ground Reference Pin (GND)), 5 (GND: Ground Reference Pin (GND)), 6 (OUT: Multiplexed I/O & Peripheral Pin OUT (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for MIC4129YME-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC4129YME-TR (SOIC-8-EP) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 2.00 × 2.00 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC4129YME-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC4129YME-TR (MICROCHIP, SOIC-8-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 3.90mm × 4.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (9/9)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VS	I/O	Multiplexed I/O & Peripheral Pin VS (General)
2	IN	I/O	Multiplexed I/O & Peripheral Pin IN (General)
3	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
4	GND	GND	Ground Reference Pin (GND)
5	GND	GND	Ground Reference Pin (GND)
6	OUT	I/O	Multiplexed I/O & Peripheral Pin OUT (General)
7	OUT	I/O	Multiplexed I/O & Peripheral Pin OUT (General)
8	VS	I/O	Multiplexed I/O & Peripheral Pin VS (General)
9	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 VS

I/O

Multiplexed I/O & Peripheral Pin VS (General)

Design note: SupplyInput:Duplicatepinsmustbeexternallyconnectedtogether

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MIC4129YME-TR (SOIC-8-EP) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MIC4129YME-TR (SOIC-8-EP) - 2. Standard Pinout (Top View)

True package pinout (9 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MIC4129YME-TR (SOIC-8-EP) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MIC4129YME-TR (SOIC-8-EP) - 4. Package Dimensions (D×E×A)

SOIC-8-EP · 3.90×4.90mm · Pitch 1.27mmExpand ›

5. Recommended Land PatternLAND PATTERN

MIC4129YME-TR (SOIC-8-EP) - 5. Recommended Land Pattern

IPC-7351B Footprint (9 Pads)Expand ›

6. Application SchematicSCHEMATIC

MIC4129YME-TR (SOIC-8-EP) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)

Showing 1–10 of 10 uncropped original figures for MIC4129

P2 · p02_fig01EXACT PACKAGE

1 | 2 | 3 | 4 | 8 | 7 | 6 | 5 | VS | OUT | OUT | GND | VS | IN | NC | GND | EPAD SOIC-8 (ME) | MLF-8 (ML)

P1 · p01_fig01769×164px

General Description

P1 · p01_fig021388×704px

MLF is a registered trademark of Amkor Technology, Inc.

P4 · p04_fig011946×1122px

Figure 1. Inverting Driver Switching Time

P5 · p05_fig012075×1478px

Typical Characteristics

P9 · p09_fig011607×964px

Figure 4. Peak Output Current Test Circuit

P9 · p09_fig01P9

Datasheet Page 9 (p09_fig01)

P10 · p10_fig01997×886px

Package Information

P10 · p10_fig021196×856px

8-Pin 3x3 MLF (ML)

P10 · p10_fig02P10

Datasheet Page 10 (p10_fig02)

Technical Specifications & Part Details (MIC4129YME-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MIC4129YME-TR (SOIC-8-EP) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 4.5V to 20V supply operation across 65°C to +150°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

4.5V to 20V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

65°C to +150°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

DC / Broadband Passive

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

4.90 × 3.90 × 1.70 mm (A1=0.06 mm)

Package family: SOIC (SOIC-8-EP)

Pin Count & Lead PitchN / e

8 Pins | Pitch e = 1.27 mm (50.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol9 auto-grouped pins

IPC-7351B Land Pattern9 pads · Pitch 1.27mm

IPC-7525 60% Solder PasteEPAD 2.00×2.00mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-8-EP)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

4.90 × 3.90 mm

Height (A) & Pitch (e)IPC-7351B

A=1.70mm · e=1.27mm

Pad Size (W × L)Level B

0.60 × 1.55 mm

Pins / Total PadsTopology

9P / 9Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit SOIC-8-EP	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MIC4129YME-TR (SOIC-8-EP)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MIC4129YME-TR (SOIC-8-EP)?

Manufactured by MICROCHIP, the MIC4129YME-TR is housed in a SOIC-8-EP package with 9 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 4.5V to 20V. Key pins include: 1 (VS: Multiplexed I/O & Peripheral Pin VS (General)), 2 (IN: Multiplexed I/O & Peripheral Pin IN (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (GND: Ground Reference Pin (GND)), 5 (GND: Ground Reference Pin (GND)), 6 (OUT: Multiplexed I/O & Peripheral Pin OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for MIC4129YME-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC4129YME-TR (SOIC-8-EP) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 2.00 × 2.00 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC4129YME-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC4129YME-TR (MICROCHIP, SOIC-8-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (9 pins) & MIC4129 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VS	Digital_IO	Signal terminal VS (I/O, 4.5V to 20V domain). Multiplexed alternate functions: VS. Supported peripheral buses: General.
2	IN	Digital_IO	Signal terminal IN (I/O, 4.5V to 20V domain). Multiplexed alternate functions: IN. Supported peripheral buses: General.
3	NC	NC	Signal terminal NC (I/O, 4.5V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6	OUT	Digital_IO	Signal terminal OUT (I/O, 4.5V to 20V domain). Multiplexed alternate functions: OUT. Supported peripheral buses: General.
7	OUT	Digital_IO	Signal terminal OUT (I/O, 4.5V to 20V domain). Multiplexed alternate functions: OUT. Supported peripheral buses: General.
8	VS	Digital_IO	Signal terminal VS (I/O, 4.5V to 20V domain). Multiplexed alternate functions: VS. Supported peripheral buses: General.
9	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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