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HV2701BD-M936 (CSP-42(5.3x5.3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

HV2701BD-M936

MICROCHIPID: C626979CSP-42(5.3x5.3) · 42 Pins · Pitch 0.60mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · HV2701BD-M936 (CSP-42(5.3x5.3))1RGND2VPP3VNN4DOUT5CLR6CLK7GND8SW15A9SW15B10LE#11VDD12SW0A13SW0B14SW14A15SW14B16DIN17SW1A18SW1B19SW13A20SW13B21SW2A42SW5A41SW5B40SW6B39SW7B38SW8A37SW9A36SW10A35SW10B34SW4B33SW4A32SW6A31SW7A30SW8B29SW9B28SW11B27SW11A26SW3B25SW3A24SW12B23SW12A22SW2BGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142E=5.30mm · Pitch e=0.60mmD=5.30mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.30mm × 5.30mm · Pitch: 0.60mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (42/42)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RGNDGNDGround Reference Pin (RGND)
2VPPI/OMultiplexed I/O & Peripheral Pin VPP (General)
3VNNI/OMultiplexed I/O & Peripheral Pin VNN (General)
4DOUTI/OMultiplexed I/O & Peripheral Pin DOUT (General)
5CLRI/OMultiplexed I/O & Peripheral Pin CLR (General)
6CLKI/OMultiplexed I/O & Peripheral Pin CLK (General)
7GNDGNDGround Reference Pin (GND)
8SW15AI/OMultiplexed I/O & Peripheral Pin SW15A (General)
9SW15BI/OMultiplexed I/O & Peripheral Pin SW15B (General)
10LE#I/OMultiplexed I/O & Peripheral Pin LE# (General)
11VDDPowerPower Supply Input (VDD — 3.0V to 5.5V)
12SW0AI/OMultiplexed I/O & Peripheral Pin SW0A (General)
13SW0BI/OMultiplexed I/O & Peripheral Pin SW0B (General)
14SW14AI/OMultiplexed I/O & Peripheral Pin SW14A (General)
15SW14BI/OMultiplexed I/O & Peripheral Pin SW14B (General)
16DINI/OMultiplexed I/O & Peripheral Pin DIN (General)
17SW1AI/OMultiplexed I/O & Peripheral Pin SW1A (General)
18SW1BI/OMultiplexed I/O & Peripheral Pin SW1B (General)
19SW13AI/OMultiplexed I/O & Peripheral Pin SW13A (General)
20SW13BI/OMultiplexed I/O & Peripheral Pin SW13B (General)
21SW2AI/OMultiplexed I/O & Peripheral Pin SW2A (General)
22SW2BI/OMultiplexed I/O & Peripheral Pin SW2B (General)
23SW12AI/OMultiplexed I/O & Peripheral Pin SW12A (General)
24SW12BI/OMultiplexed I/O & Peripheral Pin SW12B (General)
25SW3AI/OMultiplexed I/O & Peripheral Pin SW3A (General)
26SW3BI/OMultiplexed I/O & Peripheral Pin SW3B (General)
27SW11AI/OMultiplexed I/O & Peripheral Pin SW11A (General)
28SW11BI/OMultiplexed I/O & Peripheral Pin SW11B (General)
29SW9BI/OMultiplexed I/O & Peripheral Pin SW9B (General)
30SW8BI/OMultiplexed I/O & Peripheral Pin SW8B (General)
31SW7AI/OMultiplexed I/O & Peripheral Pin SW7A (General)
32SW6AI/OMultiplexed I/O & Peripheral Pin SW6A (General)
33SW4AI/OMultiplexed I/O & Peripheral Pin SW4A (General)
34SW4BI/OMultiplexed I/O & Peripheral Pin SW4B (General)
35SW10BI/OMultiplexed I/O & Peripheral Pin SW10B (General)
36SW10AI/OMultiplexed I/O & Peripheral Pin SW10A (General)
37SW9AI/OMultiplexed I/O & Peripheral Pin SW9A (General)
38SW8AI/OMultiplexed I/O & Peripheral Pin SW8A (General)
39SW7BI/OMultiplexed I/O & Peripheral Pin SW7B (General)
40SW6BI/OMultiplexed I/O & Peripheral Pin SW6B (General)
41SW5BI/OMultiplexed I/O & Peripheral Pin SW5B (General)
42SW5AI/OMultiplexed I/O & Peripheral Pin SW5A (General)
PIN 1 RGND
GND
Ground Reference Pin (RGND)
Design note: 0V electrical ground return terminal (RGND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: HV2701BD-M936 (MICROCHIP · CSP-42(5.3x5.3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
HV2701BD-M936 (CSP-42(5.3x5.3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
HV2701BD-M936 (CSP-42(5.3x5.3)) - 2. Standard Pinout (Top View)
True package pinout (42 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
HV2701BD-M936 (CSP-42(5.3x5.3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
HV2701BD-M936 (CSP-42(5.3x5.3)) - 4. Package Dimensions (D×E×A)
CSP-42(5.3x5.3) · 5.30×5.30mm · Pitch 0.60mmExpand ›
5. Recommended Land PatternLAND PATTERN
HV2701BD-M936 (CSP-42(5.3x5.3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (42 Pads)Expand ›
6. Application SchematicSCHEMATIC
HV2701BD-M936 (CSP-42(5.3x5.3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for HV2701
P1 · p01_fig01376×200px
HV2701BD-M936 (CSP-42(5.3x5.3)) — Low-Charge Injection, 16-Channel,
Low-Charge Injection, 16-Channel,
P2 · p02_fig011517×1308px
HV2701BD-M936 (CSP-42(5.3x5.3)) — Functional Block Diagram
Functional Block Diagram
P9 · p09_fig011775×1999px
HV2701BD-M936 (CSP-42(5.3x5.3)) — FIGURE 3-1: Test Circuits.
FIGURE 3-1: Test Circuits.
P9 · p09_fig01P9
HV2701BD-M936 (CSP-42(5.3x5.3)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P10 · p10_fig011249×963px
HV2701BD-M936 (CSP-42(5.3x5.3)) — FIGURE 3-2: Logic Timing Waveforms.
FIGURE 3-2: Logic Timing Waveforms.
P17 · p17_fig011041×1044px
HV2701BD-M936 (CSP-42(5.3x5.3)) — MILLIMETERS
MILLIMETERS
P19 · p19_fig011777×2725px
HV2701BD-M936 (CSP-42(5.3x5.3)) —  2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 19 | HV2601/HV2701 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: | R
 2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 19 | HV2601/HV2701 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: | R
P20 · p20_fig011777×2725px
HV2701BD-M936 (CSP-42(5.3x5.3)) — HV2601/HV2701 | DS20005391E-page 20  2015-2022 Microchip Technology Inc. and its subsidiaries | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 Contact Pad Spacing | Contact Pitch | MILLIMETERS | 0.50 BSC MIN E | MAX | 8.40 | Cont
HV2601/HV2701 | DS20005391E-page 20  2015-2022 Microchip Technology Inc. and its subsidiaries | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 Contact Pad Spacing | Contact Pitch | MILLIMETERS | 0.50 BSC MIN E | MAX | 8.40 | Cont
P20 · p20_fig01P20
HV2701BD-M936 (CSP-42(5.3x5.3)) — Datasheet Page 20 (p20_fig01)
Datasheet Page 20 (p20_fig01)
P1 · p01_fig02All Packages in PDF
HV2701BD-M936 (CSP-42(5.3x5.3)) — † Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative.
† Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative.
P11 · p11_fig01All Packages in PDF
HV2701BD-M936 (CSP-42(5.3x5.3)) —  2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 11 | † Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative. | 3 e | 3 e | XXXXXXX XXXXX^^ YYWWNNN | 3 e | HV2601
 2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 11 | † Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative. | 3 e | 3 e | XXXXXXX XXXXX^^ YYWWNNN | 3 e | HV2601

Technical Specifications & Part Details (HV2701BD-M936)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:HV2701BD-M936 (CSP-42(5.3x5.3)) is a 42-pin standard electronic & interconnect component featuring a 5.30 × 5.30 × 0.55 mm mechanical envelope (lead pitch e = 0.60 mm). Rated for 3.0V to 5.5V supply operation across 65°C to +150°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
65°C to +150°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.30 × 5.30 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (CSP-42(5.3x5.3))
Pin Count & Lead PitchN / e
42 Pins | Pitch e = 0.60 mm (23.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol42 auto-grouped pins
OK
IPC-7351B Land Pattern42 pads · Pitch 0.60mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (CSP-42(5.3x5.3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.30 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.60mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
42P / 42Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
CSP-42(5.3x5.3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HV2701BD-M936 (CSP-42(5.3x5.3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HV2701BD-M936 (CSP-42(5.3x5.3))?

Manufactured by MICROCHIP, the HV2701BD-M936 is housed in a CSP-42(5.3x5.3) package with 42 pins and a 0.60 mm lead pitch, supporting a VCC supply range of 3.0V to 5.5V. Key pins include: 1 (RGND: Ground Reference Pin (RGND)), 2 (VPP: Multiplexed I/O & Peripheral Pin VPP (General)), 3 (VNN: Multiplexed I/O & Peripheral Pin VNN (General)), 4 (DOUT: Multiplexed I/O & Peripheral Pin DOUT (General)), 5 (CLR: Multiplexed I/O & Peripheral Pin CLR (General)), 6 (CLK: Multiplexed I/O & Peripheral Pin CLK (General)).

What are the IPC-7351B PCB Footprint dimensions for HV2701BD-M936?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV2701BD-M936 (CSP-42(5.3x5.3)) has a nominal body envelope of 5.30 × 5.30 mm, pitch e = 0.60 mm, and 42 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV2701BD-M936?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV2701BD-M936 (MICROCHIP, CSP-42(5.3x5.3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (42 pins) & HV2701 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RGNDGND0V electrical ground return terminal (RGND) for internal core logic, I/O drivers, and analog sub-blocks.
2VPPDigital_IOSignal terminal VPP (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: VPP. Supported peripheral buses: General.
3VNNDigital_IOSignal terminal VNN (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: VNN. Supported peripheral buses: General.
4DOUTDigital_IOSignal terminal DOUT (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: DOUT. Supported peripheral buses: General.
5CLRDigital_IOSignal terminal CLR (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: CLR. Supported peripheral buses: General.
6CLKDigital_IOSignal terminal CLK (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
7GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
8SW15ADigital_IOSignal terminal SW15A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW15A. Supported peripheral buses: General.
9SW15BDigital_IOSignal terminal SW15B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW15B. Supported peripheral buses: General.
10LE#Digital_IOSignal terminal LE# (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: LE#. Supported peripheral buses: General.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.0V to 5.5V domain (Max rating: 5.5V).
12SW0ADigital_IOSignal terminal SW0A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW0A. Supported peripheral buses: General.
13SW0BDigital_IOSignal terminal SW0B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW0B. Supported peripheral buses: General.
14SW14ADigital_IOSignal terminal SW14A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW14A. Supported peripheral buses: General.
15SW14BDigital_IOSignal terminal SW14B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW14B. Supported peripheral buses: General.
16DINDigital_IOSignal terminal DIN (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: DIN. Supported peripheral buses: General.
17SW1ADigital_IOSignal terminal SW1A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW1A. Supported peripheral buses: General.
18SW1BDigital_IOSignal terminal SW1B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW1B. Supported peripheral buses: General.
19SW13ADigital_IOSignal terminal SW13A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW13A. Supported peripheral buses: General.
20SW13BDigital_IOSignal terminal SW13B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW13B. Supported peripheral buses: General.
21SW2ADigital_IOSignal terminal SW2A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW2A. Supported peripheral buses: General.
22SW2BDigital_IOSignal terminal SW2B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW2B. Supported peripheral buses: General.
23SW12ADigital_IOSignal terminal SW12A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW12A. Supported peripheral buses: General.
24SW12BDigital_IOSignal terminal SW12B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW12B. Supported peripheral buses: General.
25SW3ADigital_IOSignal terminal SW3A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW3A. Supported peripheral buses: General.
26SW3BDigital_IOSignal terminal SW3B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW3B. Supported peripheral buses: General.
27SW11ADigital_IOSignal terminal SW11A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW11A. Supported peripheral buses: General.
28SW11BDigital_IOSignal terminal SW11B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW11B. Supported peripheral buses: General.
29SW9BDigital_IOSignal terminal SW9B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW9B. Supported peripheral buses: General.
30SW8BDigital_IOSignal terminal SW8B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW8B. Supported peripheral buses: General.
31SW7ADigital_IOSignal terminal SW7A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW7A. Supported peripheral buses: General.
32SW6ADigital_IOSignal terminal SW6A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW6A. Supported peripheral buses: General.
33SW4ADigital_IOSignal terminal SW4A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW4A. Supported peripheral buses: General.
34SW4BDigital_IOSignal terminal SW4B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW4B. Supported peripheral buses: General.
35SW10BDigital_IOSignal terminal SW10B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW10B. Supported peripheral buses: General.
36SW10ADigital_IOSignal terminal SW10A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW10A. Supported peripheral buses: General.
37SW9ADigital_IOSignal terminal SW9A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW9A. Supported peripheral buses: General.
38SW8ADigital_IOSignal terminal SW8A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW8A. Supported peripheral buses: General.
39SW7BDigital_IOSignal terminal SW7B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW7B. Supported peripheral buses: General.
40SW6BDigital_IOSignal terminal SW6B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW6B. Supported peripheral buses: General.
41SW5BDigital_IOSignal terminal SW5B (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW5B. Supported peripheral buses: General.
42SW5ADigital_IOSignal terminal SW5A (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: SW5A. Supported peripheral buses: General.
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