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MCP1665T-E/MRA (VQFN-10-EP(2x2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

MCP1665T-E/MRA

MICROCHIPID: C623055VQFN-10-EP(2x2) · 10 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MCP1665T-E/MRA (VQFN-10-EP(2x2))1P GND2P GND3S GND4V FB5MODE10P GND9SW8SW7EN6V INGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.812.77.62.5-2.5-7.6-12.7mm
2. 2D FOOTPRINT
12345678910E=2.00mm · Pitch e=0.50mmD=2.00mm-3-2-1012343210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 2.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (10/10)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P GNDGNDGround Reference Pin (P GND)
2P GNDGNDGround Reference Pin (P GND)
3S GNDGNDGround Reference Pin (S GND)
4V FBI/OMultiplexed I/O & Peripheral Pin V FB (General)
5MODEI/OMultiplexed I/O & Peripheral Pin MODE (General)
6V INI/OMultiplexed I/O & Peripheral Pin V IN (General)
7ENISystem Enable & Hardware Reset (EN)
8SWI/OMultiplexed I/O & Peripheral Pin SW (General)
9SWI/OMultiplexed I/O & Peripheral Pin SW (General)
10P GNDGNDGround Reference Pin (P GND)
PIN 1 P GND
GND
Ground Reference Pin (P GND)
Design note: PowerGroundPin
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 25 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MCP1665T-E/MRA (MICROCHIP · VQFN-10-EP(2x2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MCP1665T-E/MRA (VQFN-10-EP(2x2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MCP1665T-E/MRA (VQFN-10-EP(2x2)) - 2. Standard Pinout (Top View)
True package pinout (10 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MCP1665T-E/MRA (VQFN-10-EP(2x2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MCP1665T-E/MRA (VQFN-10-EP(2x2)) - 4. Package Dimensions (D×E×A)
VQFN-10-EP(2x2) · 2.00×2.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
MCP1665T-E/MRA (VQFN-10-EP(2x2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (10 Pads)Expand ›
6. Application SchematicSCHEMATIC
MCP1665T-E/MRA (VQFN-10-EP(2x2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (25 figures · Page 1/3)
Showing 1–12 of 25 uncropped original figures for MCP1665
P1 · p01_fig01376×200px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — High-Voltage 3.6A Integrated Switch PFM/PWM Boost Regulator
High-Voltage 3.6A Integrated Switch PFM/PWM Boost Regulator
P1 · p01_fig021777×689px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) —  2017 Microchip Technology Inc. DS20005872A-page 1 | Applications | Package Types | *Includes Exposed Thermal Pad (EP); see Table 3-1 | SGND | PGND | FB | SW | EN | 1 | 2 | 3 4 | 9 | 8 | 7 6 VIN | SW PGND | EP | 0 | PGND | MODE | 10 | 5 |
 2017 Microchip Technology Inc. DS20005872A-page 1 | Applications | Package Types | *Includes Exposed Thermal Pad (EP); see Table 3-1 | SGND | PGND | FB | SW | EN | 1 | 2 | 3 4 | 9 | 8 | 7 6 VIN | SW PGND | EP | 0 | PGND | MODE | 10 | 5 |
P2 · p02_fig011158×686px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — D
D
P2 · p02_fig021782×1758px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — DS20005872A-page 2  2017 Microchip Technology Inc. | Best Efficiency vs. IOUT | GND | VFB | VOUT 24V, >350 mA | COUT 4x10 µF | CIN 2x10 µF | L 10 µH | SW | 383 k | 20 k EN | + | - | Li-Ion | RTOP | RBOT | VIN 3.3V-4.2V | D | VIN | MCP166
DS20005872A-page 2  2017 Microchip Technology Inc. | Best Efficiency vs. IOUT | GND | VFB | VOUT 24V, >350 mA | COUT 4x10 µF | CIN 2x10 µF | L 10 µH | SW | 383 k | 20 k EN | + | - | Li-Ion | RTOP | RBOT | VIN 3.3V-4.2V | D | VIN | MCP166
P2 · p02_fig01P2
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P8 · p08_fig011777×607px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — FIGURE 2-20: 12.0V Start-Up (VIN = VENABLE). VOUT 100 mV/div AC Coupled 20 MHz BW
FIGURE 2-20: 12.0V Start-Up (VIN = VENABLE). VOUT 100 mV/div AC Coupled 20 MHz BW
P8 · p08_fig02787×363px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — FIGURE 2-17: 12.0V VOUT Light Load PFM Mode Waveforms. VOUT 50 mV/div AC Coupled 20 MHz BW VSW 5V/div
FIGURE 2-17: 12.0V VOUT Light Load PFM Mode Waveforms. VOUT 50 mV/div AC Coupled 20 MHz BW VSW 5V/div
P8 · p08_fig03783×388px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — FIGURE 2-17: 12.0V VOUT Light Load PFM Mode Waveforms. VOUT 50 mV/div AC Coupled 20 MHz BW VSW 5V/div
FIGURE 2-17: 12.0V VOUT Light Load PFM Mode Waveforms. VOUT 50 mV/div AC Coupled 20 MHz BW VSW 5V/div
P8 · p08_fig041777×610px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — FIGURE 2-17: 12.0V VOUT Light Load PFM Mode Waveforms. VOUT 50 mV/div AC Coupled 20 MHz BW VSW 5V/div
FIGURE 2-17: 12.0V VOUT Light Load PFM Mode Waveforms. VOUT 50 mV/div AC Coupled 20 MHz BW VSW 5V/div
P8 · p08_fig05837×367px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — FIGURE 2-20: 12.0V Start-Up (VIN = VENABLE). VOUT 100 mV/div AC Coupled 20 MHz BW
FIGURE 2-20: 12.0V Start-Up (VIN = VENABLE). VOUT 100 mV/div AC Coupled 20 MHz BW
P8 · p08_fig06785×388px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — FIGURE 2-18: High-Load PWM Mode Waveforms.
FIGURE 2-18: High-Load PWM Mode Waveforms.
P8 · p08_fig071777×608px
MCP1665T-E/MRA (VQFN-10-EP(2x2)) — FIGURE 2-18: High-Load PWM Mode Waveforms.
FIGURE 2-18: High-Load PWM Mode Waveforms.
Page 1 / 3 (25 extracted figures)

Technical Specifications & Part Details (MCP1665T-E/MRA)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MCP1665T-E/MRA (VQFN-10-EP(2x2)) is a 10-pin standard electronic & interconnect component featuring a 2.00 × 2.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.9V to 5V supply operation across 65°C to +150°C with integrated PWM interfaces.
Operating Supply VoltageV_CC / V_DD
2.9V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
65°C to +150°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
500 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 2.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VQFN-10-EP(2x2))
Pin Count & Lead PitchN / e
10 Pins | Pitch e = 0.50 mm (19.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol10 auto-grouped pins
OK
IPC-7351B Land Pattern10 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VQFN-10-EP(2x2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.70 mm
Pins / Total PadsTopology
10P / 10Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VQFN-10-EP(2x2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP1665T-E/MRA (VQFN-10-EP(2x2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP1665T-E/MRA (VQFN-10-EP(2x2))?

Manufactured by MICROCHIP, the MCP1665T-E/MRA is housed in a VQFN-10-EP(2x2) package with 10 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.9V to 5V. Key pins include: 1 (P GND: Ground Reference Pin (P GND)), 2 (P GND: Ground Reference Pin (P GND)), 3 (S GND: Ground Reference Pin (S GND)), 4 (V FB: Multiplexed I/O & Peripheral Pin V FB (General)), 5 (MODE: Multiplexed I/O & Peripheral Pin MODE (General)), 6 (V IN: Multiplexed I/O & Peripheral Pin V IN (General)).

What are the IPC-7351B PCB Footprint dimensions for MCP1665T-E/MRA?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP1665T-E/MRA (VQFN-10-EP(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.50 mm, and 10 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP1665T-E/MRA?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP1665T-E/MRA (MICROCHIP, VQFN-10-EP(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (10 pins) & MCP1665 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P GNDGND0V electrical ground return terminal (P GND) for internal core logic, I/O drivers, and analog sub-blocks.
2P GNDGND0V electrical ground return terminal (P GND) for internal core logic, I/O drivers, and analog sub-blocks.
3S GNDGND0V electrical ground return terminal (S GND) for internal core logic, I/O drivers, and analog sub-blocks.
4V FBDigital_IOSignal terminal V FB (I/O, 2.9V to 5V domain). Multiplexed alternate functions: V FB. Supported peripheral buses: General.
5MODEDigital_IOSignal terminal MODE (I/O, 2.9V to 5V domain). Multiplexed alternate functions: MODE. Supported peripheral buses: General.
6V INDigital_IOSignal terminal V IN (I/O, 2.9V to 5V domain). Multiplexed alternate functions: V IN. Supported peripheral buses: General.
7ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
8SWDigital_IOSignal terminal SW (I/O, 2.9V to 5V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
9SWDigital_IOSignal terminal SW (I/O, 2.9V to 5V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
10P GNDGND0V electrical ground return terminal (P GND) for internal core logic, I/O drivers, and analog sub-blocks.
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