HV830LG-G (SOIC-8) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of HV830LG-G (SOIC-8)?

Manufactured by MICROCHIP, the HV830LG-G is housed in a SOIC-8 package with 8 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0 to 9.5V. Key pins include: 1 (VDD: Power Supply Input (VDD — 2.0 to 9.5V)), 2 (RSW-Osc: Multiplexed I/O & Peripheral Pin RSW-Osc (RTC/CLK)), 3 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 4 (LX: Multiplexed I/O & Peripheral Pin LX (General)), 5 (GND: Ground Reference Pin (GND)), 6 (AB: Multiplexed I/O & Peripheral Pin AB (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for HV830LG-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV830LG-G (SOIC-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 8 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV830LG-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV830LG-G (MICROCHIP, SOIC-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 3.90mm × 4.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VDD	Power	Power Supply Input (VDD — 2.0 to 9.5V)
2	RSW-Osc	I/O	Multiplexed I/O & Peripheral Pin RSW-Osc (RTC/CLK)
3	CS	I/O	Multiplexed I/O & Peripheral Pin CS (General)
4	LX	I/O	Multiplexed I/O & Peripheral Pin LX (General)
5	GND	GND	Ground Reference Pin (GND)
6	AB	I/O	Multiplexed I/O & Peripheral Pin AB (General)
7	VA	I/O	Multiplexed I/O & Peripheral Pin VA (General)
8	REL-Osc	I/O	Multiplexed I/O & Peripheral Pin REL-Osc (RTC/CLK)

PIN 1 VDD

Power

Power Supply Input (VDD — 2.0 to 9.5V)

Design note: Primary positive power supply input (VDD) operating in the 2.0 to 9.5V domain (Max rating: 9.5V).

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

HV830LG-G (SOIC-8) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

HV830LG-G (SOIC-8) - 2. Standard Pinout (Top View)

True package pinout (8 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

HV830LG-G (SOIC-8) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

HV830LG-G (SOIC-8) - 4. Package Dimensions (D×E×A)

SOIC-8 · 3.90×4.90mm · Pitch 1.27mmExpand ›

5. Recommended Land PatternLAND PATTERN

HV830LG-G (SOIC-8) - 5. Recommended Land Pattern

IPC-7351B Footprint (8 Pads)Expand ›

6. Application SchematicSCHEMATIC

HV830LG-G (SOIC-8) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)

Showing 1–6 of 6 uncropped original figures for HV830

P6 · p06_fig01EXACT PACKAGE

8-Lead SOIC (Narrow Body) Package Outline (LG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch

P1 · p01_fig012034×1092px

HV830LG-G (SOIC-8) — Supertex inc. | www.supertex.com | Doc. # DSFP-HV830 E072913 | Block Diagram | Disable | GND | VDD | REL-Osc | VA | CS LX | VB | RSW-Osc Q | Q | Q | Q | Output | Osc VREF | Switch | Osc | C | + | _

Supertex inc. | www.supertex.com | Doc. # DSFP-HV830 E072913 | Block Diagram | Disable | GND | VDD | REL-Osc | VA | CS LX | VB | RSW-Osc Q | Q | Q | Q | Output | Osc VREF | Switch | Osc | C | + | _

P1 · p01_fig01P1

Datasheet Page 1 (p01_fig01)

P2 · p02_fig012038×933px

Typical Thermal Resistance

P2 · p02_fig01P2

Datasheet Page 2 (p02_fig01)

P6 · p06_fig01P6

Datasheet Page 6 (p06_fig01)

Technical Specifications & Part Details (HV830LG-G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:HV830LG-G (SOIC-8) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2.0 to 9.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.0 to 9.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

DC / Broadband Passive

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

4.90 × 3.90 × 1.75 mm (A1=0.15 mm)

Package family: SOIC (SOIC-8)

Pin Count & Lead PitchN / e

8 Pins | Pitch e = 1.27 mm (50.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol8 auto-grouped pins

IPC-7351B Land Pattern8 pads · Pitch 1.27mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-8)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

4.90 × 3.90 mm

Height (A) & Pitch (e)IPC-7351B

A=1.75mm · e=1.27mm

Pad Size (W × L)Level B

0.60 × 1.55 mm

Pins / Total PadsTopology

8P / 8Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit SOIC-8	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HV830LG-G (SOIC-8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HV830LG-G (SOIC-8)?

Manufactured by MICROCHIP, the HV830LG-G is housed in a SOIC-8 package with 8 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0 to 9.5V. Key pins include: 1 (VDD: Power Supply Input (VDD — 2.0 to 9.5V)), 2 (RSW-Osc: Multiplexed I/O & Peripheral Pin RSW-Osc (RTC/CLK)), 3 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 4 (LX: Multiplexed I/O & Peripheral Pin LX (General)), 5 (GND: Ground Reference Pin (GND)), 6 (AB: Multiplexed I/O & Peripheral Pin AB (General)).

What are the IPC-7351B PCB Footprint dimensions for HV830LG-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV830LG-G (SOIC-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV830LG-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV830LG-G (MICROCHIP, SOIC-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & HV830 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0 to 9.5V domain (Max rating: 9.5V).
2	RSW-Osc	Digital_IO	Signal terminal RSW-Osc (I/O, 2.0 to 9.5V domain). Multiplexed alternate functions: RSW-Osc. Supported peripheral buses: RTC/CLK.
3	CS	Digital_IO	Signal terminal CS (I/O, 2.0 to 9.5V domain). Multiplexed alternate functions: CS. Supported peripheral buses: General.
4	LX	Digital_IO	Signal terminal LX (I/O, 2.0 to 9.5V domain). Multiplexed alternate functions: LX. Supported peripheral buses: General.
5	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6	AB	Digital_IO	Signal terminal AB (I/O, 2.0 to 9.5V domain). Multiplexed alternate functions: AB. Supported peripheral buses: General.
7	VA	Digital_IO	Signal terminal VA (I/O, 2.0 to 9.5V domain). Multiplexed alternate functions: VA. Supported peripheral buses: General.
8	REL-Osc	Digital_IO	Signal terminal REL-Osc (I/O, 2.0 to 9.5V domain). Multiplexed alternate functions: REL-Osc. Supported peripheral buses: RTC/CLK.

4D Studio: HV830LG-G Permalink: /part/C622899 MICROCHIP SOIC-8 All Packages All Manufacturers