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C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) — Symbol, Footprint IPC-7351B & 3D STEP Model

C618465

SemiconductorTFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)A1PA1A2PA2A3PA3A4PA4A5PA5A6PA6A7PA7A8PA8A9PA9A10PA10B1PB1B2PB2B3PB3B4PB4B5PB5B6PB6B7PB7B8PB8B9PB9B10PB10C1PC1C2PC2C3PC3C4PC4C5PC5C6PC6C7PC7C8PC8C9PC9C10PC10D1PD1D2PD2D3PD3D4PD4D5PD5D6PD6D7PD7D8PD8D9PD9D10PD10E1PE1E2PE2E3PE3E4PE4E5PE5E6PE6E7PE7E8PE8E9PE9E10PE10K10PK10K9PK9K8PK8K7PK7K6PK6K5PK5K4PK4K3PK3K2PK2K1PK1J10PJ10J9PJ9J8PJ8J7PJ7J6PJ6J5PJ5J4PJ4J3PJ3J2PJ2J1PJ1H10PH10H9PH9H8PH8H7PH7H6PH6H5PH5H4PH4H3PH3H2PH2H1PH1G10PG10G9PG9G8PG8G7PG7G6PG6G5PG5G4PG4G3PG3G2PB1/AD5G1PG1F10PF10F9PA18/PGMD6/AF8PF8F7PF7F6PF6F5PF5F4PF4F3PF3F2PF2F1PF1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.268.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10B1B2B3B4B5B6B7B8B9B10C1C2C3C4C5C6C7C8C9C10D1D2D3D4D5D6D7D8D9D10E1E2E3E4E5E6E7E8E9E10F1F2F3F4F5F6F7F8F9F10G1G2G3G4G5G6G7G8G9G10H1H2H3H4H5H6H7H8H9H10J1J2J3J4J5J6J7J8J9J10K1K2K3K4K5K6K7K8K9K10E=9.00mm · Pitch e=0.80mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
A2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
A3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
A4PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
A5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
A6PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
A7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
A8PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
A9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
A10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
B1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
B2PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
B3PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
B4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
B6PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
B7PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
B8PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
B9PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
B10PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
C1PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
C2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
C3PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
C4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
C5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
C6PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
C7PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
C8PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
C9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
C10PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
D1PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D2PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
D3PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
D4PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
D5PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
D6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
D7PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
D8PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
D9PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
D10PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
E1PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
E2PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
E3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
E4PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
E5PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
E6PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
E7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
E8PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
E9PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
E10PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
F1PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
F2PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
F3PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
F4PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
F5PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
F6PF6I/OMultiplexed I/O & Peripheral Pin PF6 (General)
F7PF7I/OMultiplexed I/O & Peripheral Pin PF7 (General)
F8PF8I/OMultiplexed I/O & Peripheral Pin PF8 (General)
F9PA18/PGMD6/AD1I/OMultiplexed I/O & Peripheral Pin PA18/PGMD6/AD1 (General)
F10PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
G1PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
G2PB1/AD5I/OMultiplexed I/O & Peripheral Pin PB1/AD5 (General)
G3PG3I/OMultiplexed I/O & Peripheral Pin PG3 (General)
G4PG4I/OMultiplexed I/O & Peripheral Pin PG4 (General)
G5PG5I/OMultiplexed I/O & Peripheral Pin PG5 (General)
G6PG6I/OMultiplexed I/O & Peripheral Pin PG6 (General)
G7PG7I/OMultiplexed I/O & Peripheral Pin PG7 (General)
G8PG8I/OMultiplexed I/O & Peripheral Pin PG8 (General)
G9PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
G10PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
H1PH1I/OMultiplexed I/O & Peripheral Pin PH1 (General)
H2PH2I/OMultiplexed I/O & Peripheral Pin PH2 (General)
H3PH3I/OMultiplexed I/O & Peripheral Pin PH3 (General)
H4PH4I/OMultiplexed I/O & Peripheral Pin PH4 (General)
H5PH5I/OMultiplexed I/O & Peripheral Pin PH5 (General)
H6PH6I/OMultiplexed I/O & Peripheral Pin PH6 (General)
H7PH7I/OMultiplexed I/O & Peripheral Pin PH7 (General)
H8PH8I/OMultiplexed I/O & Peripheral Pin PH8 (General)
H9PH9I/OMultiplexed I/O & Peripheral Pin PH9 (General)
H10PH10I/OMultiplexed I/O & Peripheral Pin PH10 (General)
J1PJ1I/OMultiplexed I/O & Peripheral Pin PJ1 (General)
J2PJ2I/OMultiplexed I/O & Peripheral Pin PJ2 (General)
J3PJ3I/OMultiplexed I/O & Peripheral Pin PJ3 (General)
J4PJ4I/OMultiplexed I/O & Peripheral Pin PJ4 (General)
J5PJ5I/OMultiplexed I/O & Peripheral Pin PJ5 (General)
J6PJ6I/OMultiplexed I/O & Peripheral Pin PJ6 (General)
J7PJ7I/OMultiplexed I/O & Peripheral Pin PJ7 (General)
J8PJ8I/OMultiplexed I/O & Peripheral Pin PJ8 (General)
J9PJ9I/OMultiplexed I/O & Peripheral Pin PJ9 (General)
J10PJ10I/OMultiplexed I/O & Peripheral Pin PJ10 (General)
K1PK1I/OMultiplexed I/O & Peripheral Pin PK1 (General)
K2PK2I/OMultiplexed I/O & Peripheral Pin PK2 (General)
K3PK3I/OMultiplexed I/O & Peripheral Pin PK3 (General)
K4PK4I/OMultiplexed I/O & Peripheral Pin PK4 (General)
K5PK5I/OMultiplexed I/O & Peripheral Pin PK5 (General)
K6PK6I/OMultiplexed I/O & Peripheral Pin PK6 (General)
K7PK7I/OMultiplexed I/O & Peripheral Pin PK7 (General)
K8PK8I/OMultiplexed I/O & Peripheral Pin PK8 (General)
K9PK9I/OMultiplexed I/O & Peripheral Pin PK9 (General)
K10PK10I/OMultiplexed I/O & Peripheral Pin PK10 (General)
PIN A1 PA1
I/O
Multiplexed I/O & Peripheral Pin PA1 (General)
Design note: Signal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C618465 (Semiconductor · TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 4. Package Dimensions (D×E×A)
TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB · 9.00×9.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C618465)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) is a 100-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.40 × 0.40 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)?

Manufactured by Semiconductor, the C618465 is housed in a TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB package with 100 pins and a 0.80 mm lead pitch. Key pins include: A1 (PA1: Multiplexed I/O & Peripheral Pin PA1 (General)), A2 (PA2: Multiplexed I/O & Peripheral Pin PA2 (General)), A3 (PA3: Multiplexed I/O & Peripheral Pin PA3 (General)), A4 (PA4: Multiplexed I/O & Peripheral Pin PA4 (General)), A5 (PA5: Multiplexed I/O & Peripheral Pin PA5 (General)), A6 (PA6: Multiplexed I/O & Peripheral Pin PA6 (General)).

What are the IPC-7351B PCB Footprint dimensions for C618465?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C618465 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C618465?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C618465 (Semiconductor, TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & C618465 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
A2PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
A3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
A4PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
A5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
A6PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
A7PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
A8PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
A9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
A10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
B1PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
B2PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
B3PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
B4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
B6PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B7PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
B8PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B9PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
B10PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
C1PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
C2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
C3PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
C4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
C5PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
C6PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
C7PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
C8PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
C9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
C10PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
D1PD1Digital_IOSignal terminal PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D2PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
D3PD3Digital_IOSignal terminal PD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
D4PD4Digital_IOSignal terminal PD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
D5PD5Digital_IOSignal terminal PD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
D6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
D7PD7Digital_IOSignal terminal PD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
D8PD8Digital_IOSignal terminal PD8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
D9PD9Digital_IOSignal terminal PD9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
D10PD10Digital_IOSignal terminal PD10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
E1PE1Digital_IOSignal terminal PE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
E2PE2Digital_IOSignal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
E3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
E4PE4Digital_IOSignal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
E5PE5Digital_IOSignal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
E6PE6Digital_IOSignal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
E7PE7Digital_IOSignal terminal PE7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
E8PE8Digital_IOSignal terminal PE8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
E9PE9Digital_IOSignal terminal PE9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General.
E10PE10Digital_IOSignal terminal PE10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
F1PF1Digital_IOSignal terminal PF1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
F2PF2Digital_IOSignal terminal PF2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
F3PF3Digital_IOSignal terminal PF3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
F4PF4Digital_IOSignal terminal PF4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
F5PF5Digital_IOSignal terminal PF5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
F6PF6Digital_IOSignal terminal PF6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF6. Supported peripheral buses: General.
F7PF7Digital_IOSignal terminal PF7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF7. Supported peripheral buses: General.
F8PF8Digital_IOSignal terminal PF8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF8. Supported peripheral buses: General.
F9PA18/PGMD6/AD1Digital_IOSignal terminal PA18/PGMD6/AD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA18/PGMD6/AD1. Supported peripheral buses: General.
F10PF10Digital_IOSignal terminal PF10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General.
G1PG1Digital_IOSignal terminal PG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG1. Supported peripheral buses: General.
G2PB1/AD5Digital_IOSignal terminal PB1/AD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/AD5. Supported peripheral buses: General.
G3PG3Digital_IOSignal terminal PG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG3. Supported peripheral buses: General.
G4PG4Digital_IOSignal terminal PG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG4. Supported peripheral buses: General.
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