- · 37P
Synchronized Pinout (Symbol / 2D / 3D) (37/37)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | GND | GND | Ground Reference Pin (GND) |
| 2 | SPI_CFG | I/O | Multiplexed I/O & Peripheral Pin SPI_CFG (SPI) |
| 3 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 4 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 5 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 6 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 7 | RESETN | I | System Enable & Hardware Reset (RESETN) |
| 8 | BT_TXD | I/O | Multiplexed I/O & Peripheral Pin BT_TXD (UART, SPI) |
| 9 | BT_RXD | I/O | Multiplexed I/O & Peripheral Pin BT_RXD (UART, SPI) |
| 10 | I2C_SDAS_ | I/O | Multiplexed I/O & Peripheral Pin I2C_SDAS_ (I2C) |
| 11 | I2C_SCLS_ | I/O | Multiplexed I/O & Peripheral Pin I2C_SCLS_ (I2C) |
| 12 | VDDIO | Power | Power Supply Input (VDDIO — 2.7V to 3.6V) |
| 13 | GND | GND | Ground Reference Pin (GND) |
| 14 | GPIO3 | I/O | Multiplexed I/O & Peripheral Pin GPIO3 (General) |
| 15 | GPIO4 | I/O | Multiplexed I/O & Peripheral Pin GPIO4 (General) |
| 16 | UART_TXD | I/O | Multiplexed I/O & Peripheral Pin UART_TXD (UART) |
| 17 | UART_RXD | I/O | Multiplexed I/O & Peripheral Pin UART_RXD (UART) |
| 18 | VBAT | Power | Power Supply Input (VBAT — 2.7V to 3.6V) |
| 19 | CHIP_EN | I/O | Multiplexed I/O & Peripheral Pin CHIP_EN (General) |
| 20 | RTC_CLK | I/O | Multiplexed I/O & Peripheral Pin RTC_CLK (RTC/CLK) |
| 21 | GND | GND | Ground Reference Pin (GND) |
| 22 | GPIO8 | I/O | Multiplexed I/O & Peripheral Pin GPIO8 (General) |
| 23 | SPI_SCK | I/O | Multiplexed I/O & Peripheral Pin SPI_SCK (SPI) |
| 24 | SPI_MISO | I/O | Multiplexed I/O & Peripheral Pin SPI_MISO (SPI) |
| 25 | SPI_SSN | I/O | Multiplexed I/O & Peripheral Pin SPI_SSN (SPI) |
| 26 | SPI_MOSI | I/O | Multiplexed I/O & Peripheral Pin SPI_MOSI (SPI) |
| 27 | GPIO7 | I/O | Multiplexed I/O & Peripheral Pin GPIO7 (General) |
| 28 | GND | GND | Ground Reference Pin (GND) |
| 29 | GPIO17 | I/O | Multiplexed I/O & Peripheral Pin GPIO17 (General) |
| 30 | GPIO18 | I/O | Multiplexed I/O & Peripheral Pin GPIO18 (General) |
| 31 | GPIO19 | I/O | Multiplexed I/O & Peripheral Pin GPIO19 (General) |
| 32 | GPIO20 | I/O | Multiplexed I/O & Peripheral Pin GPIO20 (General) |
| 33 | IRQN | I/O | Multiplexed I/O & Peripheral Pin IRQN (General) |
| 34 | I2C_SCLM_ | I/O | Multiplexed I/O & Peripheral Pin I2C_SCLM_ (I2C) |
| 35 | I2C_SDAM_ | I/O | Multiplexed I/O & Peripheral Pin I2C_SDAM_ (I2C) |
| 36 | GND | GND | Ground Reference Pin (GND) |
| 37 | PADDLEVSS | GND | Ground Reference Pin (PADDLEVSS) |
PIN 1 GND
GNDGround Reference Pin (GND)
Design note: Groundpin
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (37 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SMD-36P · 14.73×22.43mm · Pitch 1.20mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (37 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for ATWINC3400
P1 · p01_fig01456×280px
P7 · p07_fig011257×1356px
P30 · p30_fig011336×379px
P33 · p33_fig011669×1083px
P33 · p33_fig01P33
P35 · p35_fig011648×1809px
P35 · p35_fig01P35
P36 · p36_fig011012×648px
P36 · p36_fig021431×1176px
P38 · p38_fig011001×641px
P38 · p38_fig021593×1229px
P38 · p38_fig02P38
Technical Specifications & Part Details (ATWINC3400-MR210CA122-T)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ATWINC3400-MR210CA122-T (SMD-36P) is a 36-pin wireless wi-fi / bluetooth le soc module featuring a 22.43 × 14.73 × 2.40 mm mechanical envelope (lead pitch e = 1.20 mm). Rated for 2.7V to 3.6V supply operation across -40°C to +85°C with integrated Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32.768 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
22.43 × 14.73 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD-36P)
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 1.20 mm (47.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol37 auto-grouped pins
IPC-7351B Land Pattern37 pads · Pitch 1.20mm
IPC-7525 60% Solder PasteEPAD 4.40×4.40mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ATWINC3400 (6)
SMD-36P · 37P
37P22.4×14.7×2.40mmP=1.2mm
ATWINC3400 (SMD-36P)
SMD-36P · 37P
37P22.4×14.7×2.40mmP=1.2mm
ATWINC3400 (SMD-36P)
SMD-36P · 37P
37P22.4×14.7×2.40mmP=1.2mm
ATWINC3400 (SMD-36P)
SMD-36P · 37P
37P22.4×14.7×2.40mmP=1.2mm
ATWINC3400 (SMD-36P)
SMD-36P · 37P
37P22.4×14.7×2.40mmP=1.2mm
ATWINC3400 (SMD-36P)
Mechanical Dimensions & Land Pattern (SMD-36P)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
22.43 × 14.73 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=1.20mm
Pad Size (W × L)Level B
0.81 × 1.88 mm
Pins / Total PadsTopology
37P / 37Pad (CASTELLATED_MODULE)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SMD-36P | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ATWINC3400-MR210CA122-T (SMD-36P)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ATWINC3400-MR210CA122-T (SMD-36P)?
Manufactured by MICROCHIP, the ATWINC3400-MR210CA122-T is housed in a SMD-36P package with 37 pins and a 1.20 mm lead pitch, supporting a VCC supply range of 2.7V to 3.6V. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (SPI_CFG: Multiplexed I/O & Peripheral Pin SPI_CFG (SPI)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).
What are the IPC-7351B PCB Footprint dimensions for ATWINC3400-MR210CA122-T?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATWINC3400-MR210CA122-T (SMD-36P) has a nominal body envelope of 14.73 × 22.43 mm, pitch e = 1.20 mm, and 37 copper pads plus a central exposed thermal pad (EPAD) of 4.40 × 4.40 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATWINC3400-MR210CA122-T?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATWINC3400-MR210CA122-T (MICROCHIP, SMD-36P) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (37 pins) & ATWINC3400 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 2 | SPI_CFG | Digital_IO | Signal terminal SPI_CFG (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI_CFG. Supported peripheral buses: SPI. |
| 3 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 4 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 5 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 6 | NC | NC | Signal terminal NC (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 7 | RESETN | Digital_IO | Active-low hardware reset terminal (RESETN): pulling this pin Low resets the processor core and peripherals. |
| 8 | BT_TXD | Digital_IO | Signal terminal BT_TXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI. |
| 9 | BT_RXD | Digital_IO | Signal terminal BT_RXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIISTHEDATAANDCONTROLINTERFACEWITHTHE. Supported peripheral buses: UART, SPI. |
| 10 | I2C_SDAS_ | Digital_IO | Signal terminal I2C_SDAS_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SDAS_. Supported peripheral buses: I2C. |
| 11 | I2C_SCLS_ | Digital_IO | Signal terminal I2C_SCLS_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SCLS_. Supported peripheral buses: I2C. |
| 12 | VDDIO | Power_In | Primary positive power supply input (VDDIO) operating in the 2.7V to 3.6V domain (Max rating: 3.6V). |
| 13 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | GPIO3 | Digital_IO | Signal terminal GPIO3 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General. |
| 15 | GPIO4 | Digital_IO | Signal terminal GPIO4 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General. |
| 16 | UART_TXD | Digital_IO | Signal terminal UART_TXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: UART_TXD. Supported peripheral buses: UART. |
| 17 | UART_RXD | Digital_IO | Signal terminal UART_RXD (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: UART_RXD. Supported peripheral buses: UART. |
| 18 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 2.7V to 3.6V domain (Max rating: 3.6V). |
| 19 | CHIP_EN | Digital_IO | Signal terminal CHIP_EN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General. |
| 20 | RTC_CLK | Digital_IO | Signal terminal RTC_CLK (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: RTC_CLK. Supported peripheral buses: RTC/CLK. |
| 21 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 22 | GPIO8 | Digital_IO | Signal terminal GPIO8 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General. |
| 23 | SPI_SCK | Digital_IO | Signal terminal SPI_SCK (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPICLOCKPIN. Supported peripheral buses: SPI. |
| 24 | SPI_MISO | Digital_IO | Signal terminal SPI_MISO (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIMISO. Supported peripheral buses: SPI. |
| 25 | SPI_SSN | Digital_IO | Signal terminal SPI_SSN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPI_SSN. Supported peripheral buses: SPI. |
| 26 | SPI_MOSI | Digital_IO | Signal terminal SPI_MOSI (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: SPIMOSI. Supported peripheral buses: SPI. |
| 27 | GPIO7 | Digital_IO | Signal terminal GPIO7 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General. |
| 28 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 29 | GPIO17 | Digital_IO | Signal terminal GPIO17 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO17. Supported peripheral buses: General. |
| 30 | GPIO18 | Digital_IO | Signal terminal GPIO18 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General. |
| 31 | GPIO19 | Digital_IO | Signal terminal GPIO19 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: General. |
| 32 | GPIO20 | Digital_IO | Signal terminal GPIO20 (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: GPIO20. Supported peripheral buses: General. |
| 33 | IRQN | Digital_IO | Signal terminal IRQN (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: IRQN. Supported peripheral buses: General. |
| 34 | I2C_SCLM_ | Digital_IO | Signal terminal I2C_SCLM_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SCLM_. Supported peripheral buses: I2C. |
| 35 | I2C_SDAM_ | Digital_IO | Signal terminal I2C_SDAM_ (I/O, 2.7V to 3.6V domain). Multiplexed alternate functions: I2C_SDAM_. Supported peripheral buses: I2C. |
| 36 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 37 | PADDLEVSS | GND | 0V electrical ground return terminal (PADDLEVSS) for internal core logic, I/O drivers, and analog sub-blocks. |