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ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATBTLC1000A-UU-T

MICROCHIPID: C5949683WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A · 31 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A)A2VDDIOA4XO_PA6VDD VCO&VDD_B1AO_GPIO0_B3VDDIO_SWITCHB5XO_NB7RFIOC2RTC_CLKP_C4TPPC6VDD_RFD1RTC_CLKN_D3LP_GPIO13_D5LP_GPIO0_D7RFGNDE2CHIP_ENE4VSSJ6LP_GPIO8_J4LP_GPIO10_J2VSWH7LP_GPIO3_H5LP_GPIO9_H3GND_BUCKH1VDDC_PD4G6LP_GPIO2_G4LP_GPIO12_G2VBATT_BUCKF7LP_GPIO1_F5LP_GPIO11_F3GPIO_MS1F1LP_LDOOUT1P2E6VDD_AMSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
A2A4A6B1B3B5B7C2C4C6D1D3D5D7E2E4E6F1F3F5F7G2G4G6H1H3H5H7J2J4J6E=2.20mm · Pitch e=0.35mmD=2.10mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.20mm × 2.10mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (31/31)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
A4XO_PI/OMultiplexed I/O & Peripheral Pin XO_P (RTC/CLK)
A6VDD VCO&VDD_SXDIG_PowerPower Supply Input (VDD VCO&VDD_SXDIG_ — 3.3V / 5.0V Standard Logic)
B1AO_GPIO0_I/OMultiplexed I/O & Peripheral Pin AO_GPIO0_ (General)
B3VDDIO_SWITCHPowerPower Supply Input (VDDIO_SWITCH — 3.3V / 5.0V Standard Logic)
B5XO_NI/OMultiplexed I/O & Peripheral Pin XO_N (RTC/CLK)
B7RFIOI/OMultiplexed I/O & Peripheral Pin RFIO (General)
C2RTC_CLKP_I/OMultiplexed I/O & Peripheral Pin RTC_CLKP_ (RTC/CLK)
C4TPPI/OMultiplexed I/O & Peripheral Pin TPP (General)
C6VDD_RFPowerPower Supply Input (VDD_RF — 3.3V / 5.0V Standard Logic)
D1RTC_CLKN_I/OMultiplexed I/O & Peripheral Pin RTC_CLKN_ (RTC/CLK)
D3LP_GPIO13_I/OMultiplexed I/O & Peripheral Pin LP_GPIO13_ (SPI)
D5LP_GPIO0_I/OMultiplexed I/O & Peripheral Pin LP_GPIO0_ (General)
D7RFGNDGNDGround Reference Pin (RFGND)
E2CHIP_ENI/OMultiplexed I/O & Peripheral Pin CHIP_EN (General)
E4VSSGNDGround Reference Pin (VSS)
E6VDD_AMSPowerPower Supply Input (VDD_AMS — 3.3V / 5.0V Standard Logic)
F1LP_LDOOUT1P2__I/OMultiplexed I/O & Peripheral Pin LP_LDOOUT1P2__ (General)
F3GPIO_MS1I/OMultiplexed I/O & Peripheral Pin GPIO_MS1 (ADC)
F5LP_GPIO11_I/OMultiplexed I/O & Peripheral Pin LP_GPIO11_ (SPI)
F7LP_GPIO1_I/OMultiplexed I/O & Peripheral Pin LP_GPIO1_ (General)
G2VBATT_BUCKPowerPower Supply Input (VBATT_BUCK — 3.3V / 5.0V Standard Logic)
G4LP_GPIO12_I/OMultiplexed I/O & Peripheral Pin LP_GPIO12_ (SPI)
G6LP_GPIO2_I/OMultiplexed I/O & Peripheral Pin LP_GPIO2_ (UART)
H1VDDC_PD4PowerRegulated Power Output (VDDC_PD4 — 3.3V / 5.0V Standard Logic)
H3GND_BUCKGNDGround Reference Pin (GND_BUCK)
H5LP_GPIO9_I/OMultiplexed I/O & Peripheral Pin LP_GPIO9_ (I2C)
H7LP_GPIO3_I/OMultiplexed I/O & Peripheral Pin LP_GPIO3_ (UART)
J2VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
J4LP_GPIO10_I/OMultiplexed I/O & Peripheral Pin LP_GPIO10_ (SPI)
J6LP_GPIO8_I/OMultiplexed I/O & Peripheral Pin LP_GPIO8_ (I2C)
PIN A2 VDDIO
Power
Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
Design note: I/OSupply canbelessthanorequaltoVBATT BUCK ,_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATBTLC1000A-UU-T (MICROCHIP · WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) - 2. Standard Pinout (Top View)
True package pinout (31 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) - 4. Package Dimensions (D×E×A)
WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A · 2.20×2.10mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) - 5. Recommended Land Pattern
IPC-7351B Footprint (31 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for ATBTLC1000A
P6 · p06_fig01EXACT PACKAGE
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) — Figure 4-1. ATBTLC1000 WLCSP Pin Assignment
Figure 4-1. ATBTLC1000 WLCSP Pin Assignment
P8 · p08_fig01EXACT PACKAGE
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) — Figure 5-1. ATBTLC1000 31L WLCSP Package Outline Drawing
Figure 5-1. ATBTLC1000 31L WLCSP Package Outline Drawing
P5 · p05_fig011772×1009px
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) — Figure 3-1. ATBTLC1000 Block Diagram
Figure 3-1. ATBTLC1000 Block Diagram
P8 · p08_fig01P8
ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) — Datasheet Page 8 (p08_fig01)
Datasheet Page 8 (p08_fig01)

Technical Specifications & Part Details (ATBTLC1000A-UU-T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) is a 31-pin standard electronic & interconnect component featuring a 2.10 × 2.20 × 0.55 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, UART, SPI, I2C, ADC, PWM, JTAG / SWD, CAN, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.10 × 2.20 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A)
Pin Count & Lead PitchN / e
31 Pins | Pitch e = 0.35 mm (13.9 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, UART, SPI, I2C, ADC, PWM, JTAG / SWD, CAN, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol31 auto-grouped pins
OK
IPC-7351B Land Pattern31 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.10 × 2.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.35mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
31P / 31Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A)?

Manufactured by MICROCHIP, the ATBTLC1000A-UU-T is housed in a WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A package with 31 pins and a 0.35 mm lead pitch. Key pins include: A2 (VDDIO: Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)), A4 (XO_P: Multiplexed I/O & Peripheral Pin XO_P (RTC/CLK)), A6 (VDD VCO&VDD_SXDIG_: Power Supply Input (VDD VCO&VDD_SXDIG_ — 3.3V / 5.0V Standard Logic)), B1 (AO_GPIO0_: Multiplexed I/O & Peripheral Pin AO_GPIO0_ (General)), B3 (VDDIO_SWITCH: Power Supply Input (VDDIO_SWITCH — 3.3V / 5.0V Standard Logic)), B5 (XO_N: Multiplexed I/O & Peripheral Pin XO_N (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for ATBTLC1000A-UU-T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATBTLC1000A-UU-T (WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) has a nominal body envelope of 2.20 × 2.10 mm, pitch e = 0.35 mm, and 31 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATBTLC1000A-UU-T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATBTLC1000A-UU-T (MICROCHIP, WLCSP-31_L2.2-W2.1_ATMEL_ATBTL1000A) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (31 pins) & ATBTLC1000A Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A4XO_PDigital_IOSignal terminal XO_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO_P. Supported peripheral buses: RTC/CLK.
A6VDD VCO&VDD_SXDIG_Power_InPrimary positive power supply input (VDD VCO&VDD_SXDIG_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B1AO_GPIO0_Digital_IOSignal terminal AO_GPIO0_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AO_GPIO0_. Supported peripheral buses: General.
B3VDDIO_SWITCHPower_InPrimary positive power supply input (VDDIO_SWITCH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B5XO_NDigital_IOSignal terminal XO_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO_N. Supported peripheral buses: RTC/CLK.
B7RFIORF_50OhmSignal terminal RFIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RFIO. Supported peripheral buses: General.
C2RTC_CLKP_Digital_IOSignal terminal RTC_CLKP_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTC_CLKP_. Supported peripheral buses: RTC/CLK.
C4TPPDigital_IOSignal terminal TPP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TPP. Supported peripheral buses: General.
C6VDD_RFPower_InPrimary positive power supply input (VDD_RF) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D1RTC_CLKN_Digital_IOSignal terminal RTC_CLKN_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTC_CLKN_. Supported peripheral buses: RTC/CLK.
D3LP_GPIO13_Digital_IOSignal terminal LP_GPIO13_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIMISO, SPIFLASHRXD. Supported peripheral buses: SPI.
D5LP_GPIO0_Digital_IOSignal terminal LP_GPIO0_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LP_GPIO0_. Supported peripheral buses: General.
D7RFGNDGND0V electrical ground return terminal (RFGND) for internal core logic, I/O drivers, and analog sub-blocks.
E2CHIP_ENDigital_IOSignal terminal CHIP_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General.
E4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E6VDD_AMSPower_InPrimary positive power supply input (VDD_AMS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F1LP_LDOOUT1P2__Digital_IOSignal terminal LP_LDOOUT1P2__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LP_LDOOUT1P2__. Supported peripheral buses: General.
F3GPIO_MS1Digital_IOSignal terminal GPIO_MS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO_MS1. Supported peripheral buses: ADC.
F5LP_GPIO11_Digital_IOSignal terminal LP_GPIO11_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIMOSI, SPIFLASHTXD. Supported peripheral buses: SPI.
F7LP_GPIO1_Digital_IOSignal terminal LP_GPIO1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LP_GPIO1_. Supported peripheral buses: General.
G2VBATT_BUCKPower_InPrimary positive power supply input (VBATT_BUCK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
G4LP_GPIO12_Digital_IOSignal terminal LP_GPIO12_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPISSN, SPIFLASHSSN. Supported peripheral buses: SPI.
G6LP_GPIO2_Digital_IOSignal terminal LP_GPIO2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LP_GPIO2_. Supported peripheral buses: UART.
H1VDDC_PD4Power_OutRegulated power output rail (VDDC_PD4) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H3GND_BUCKGND0V electrical ground return terminal (GND_BUCK) for internal core logic, I/O drivers, and analog sub-blocks.
H5LP_GPIO9_Digital_IOSignal terminal LP_GPIO9_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SCL. Supported peripheral buses: I2C.
H7LP_GPIO3_Digital_IOSignal terminal LP_GPIO3_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LP_GPIO3_. Supported peripheral buses: UART.
J2VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
J4LP_GPIO10_Digital_IOSignal terminal LP_GPIO10_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPISCK, SPIFLASHSCK. Supported peripheral buses: SPI.
J6LP_GPIO8_Digital_IOSignal terminal LP_GPIO8_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SDA. Supported peripheral buses: I2C.
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