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STM32G0B1RBI3N (UFBGA-64(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32G0B1RBI3N

STID: C5931904UFBGA-64(5x5) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32G0B1RBI3N (UFBGA-64(5x5))A1PC11A2PC10A3PB7A4PB6A5PD6A6PD2A7PD0A8PC8B1PC15 - OSC32B2PC12B3PB8B4PB3B5PD5B6PD1B7PC9B8PA12[PA10]C1PC14 - OSC32C2PC13C3PB9C4PB4C5PD4C6PA15C7PA14BOOT0 -C8PA11[PA9]D1VDD/VDDAD2VREF+D3VBATD4PB5D5PD3D6PA10D7PA13D8VDDIO2H8PB11H7PB2H6PC5H5PC4H4PA4H3PA1H2PA0H1PC3G8PB13G7PB12G6PB10G5PB1G4PA5G3PA2G2PC2G1PF1 - OSC_OUF8PA8F7PB15F6PB14F5PB0F4PA6F3PA3F2PC1F1PF0OSC IN -_E8VSSE7PC6E6PA9E5PC7E4PA7E3PC0E2PF2NRST -E1VSS/VSSAGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1A2B2C2D2E2F2G2H2A3B3C3D3E3F3G3H3A4B4C4D4E4F4G4H4A5B5C5D5E5F5G5H5A6B6C6D6E6F6G6H6A7B7C7D7E7F7G7H7A8B8C8D8E8F8G8H8E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, PWM)
A2PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, PWM)
A3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, SPI, I2C)
A4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, SPI)
A5PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART, SPI)
A6PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
A7PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI)
A8PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART, PWM)
B1PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
B2PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
B3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, SPI, I2C)
B4PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART, SPI, I2C)
B5PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART, SPI)
B6PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI)
B7PC9I/OMultiplexed I/O & Peripheral Pin PC9 (USB, UART)
B8PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (USB, UART, SPI, I2C)
C1PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
C2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
C3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C, PWM)
C4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (UART, SPI, I2C)
C5PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, SPI)
C6PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, I2C, RTC/CLK)
C7PA14BOOT0 -I/OMultiplexed I/O & Peripheral Pin PA14BOOT0 - (UART, SWD/JTAG)
C8PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (USB, UART, SPI, I2C)
D1VDD/VDDAPowerPower Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))
D2VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
D3VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI)
D5PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
D6PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, SPI, I2C)
D7PA13I/OMultiplexed I/O & Peripheral Pin PA13 (USB, SWD/JTAG)
D8VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
E1VSS/VSSAGNDGround Reference Pin (VSS/VSSA)
E2PF2NRST -I/OMultiplexed I/O & Peripheral Pin PF2NRST - (UART, RTC/CLK)
E3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (UART, I2C)
E4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, ADC)
E5PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
E6PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, I2C, RTC/CLK)
E7PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
E8VSSGNDGround Reference Pin (VSS)
F1PF0OSC IN -_I/OMultiplexed I/O & Peripheral Pin PF0OSC IN -_ (RTC/CLK)
F2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (UART, I2C)
F3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, SPI)
F4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, I2C, ADC)
F5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI)
F6PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C)
F7PB15I/OMultiplexed I/O & Peripheral Pin PB15 (UART, SPI)
F8PA8I/OMultiplexed I/O & Peripheral Pin PA8 (SPI, I2C, RTC/CLK)
G1PF1 - OSC_OUTI/OMultiplexed I/O & Peripheral Pin PF1 - OSC_OUT (RTC/CLK)
G2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, CAN)
G3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, SPI, ADC)
G4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
G5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, PWM)
G6PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, ADC)
G7PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, ADC)
G8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C)
H1PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI)
H2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC)
H3PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, I2C)
H4PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
H5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART)
H6PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART)
H7PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, RTC/CLK)
H8PB11I/OMultiplexed I/O & Peripheral Pin PB11 (SPI, I2C, ADC)
PIN A1 PC11
I/O
Multiplexed I/O & Peripheral Pin PC11 (UART, PWM)
Design note: Alt: USART3 RX USART4 RX TIM1_CH4SPI3MISO ,_ ,_ ,_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32G0B1RBI3N (ST · UFBGA-64(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32G0B1RBI3N (UFBGA-64(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32G0B1RBI3N (UFBGA-64(5x5)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32G0B1RBI3N (UFBGA-64(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32G0B1RBI3N (UFBGA-64(5x5)) - 4. Package Dimensions (D×E×A)
UFBGA-64(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32G0B1RBI3N (UFBGA-64(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32G0B1RBI3N (UFBGA-64(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32G0B1KEU / STM32G0B1RBI
P1 · p01_fig01EXACT PACKAGE
STM32G0B1RBI3N (UFBGA-64(5x5)) — Arm® Cortex®-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM,
Arm® Cortex®-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM,
P1 · p01_fig02EXACT PACKAGE
STM32G0B1RBI3N (UFBGA-64(5x5)) — 5 × 5 mm
5 × 5 mm
P40 · p40_fig01EXACT PACKAGE
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 7. STM32G0B1RxI UFBGA64 pinout 1 2 3 4 5 6 7 8
Figure 7. STM32G0B1RxI UFBGA64 pinout 1 2 3 4 5 6 7 8
P139 · p139_fig01EXACT PACKAGE
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 52. UFBGA64 package outline
Figure 52. UFBGA64 package outline
P140 · p140_fig01EXACT PACKAGE
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 53. Recommended footprint for UFBGA64 package
Figure 53. Recommended footprint for UFBGA64 package
P1 · p01_fig02P1
STM32G0B1RBI3N (UFBGA-64(5x5)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P36 · p36_fig011546×1456px
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 3. STM32G0B1VxT LQFP100 pinout
Figure 3. STM32G0B1VxT LQFP100 pinout
P37 · p37_fig011548×1573px
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 4. STM32G0B1VxI UFBGA100 pinout
Figure 4. STM32G0B1VxI UFBGA100 pinout
P65 · p65_fig011546×1547px
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 15. Power supply scheme
Figure 15. Power supply scheme
P65 · p65_fig01P65
STM32G0B1RBI3N (UFBGA-64(5x5)) — Datasheet Page 65 (p65_fig01)
Datasheet Page 65 (p65_fig01)
P84 · p84_fig011546×702px
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 20. Typical application with an 8 MHz crystal
Figure 20. Typical application with an 8 MHz crystal
P85 · p85_fig011546×702px
STM32G0B1RBI3N (UFBGA-64(5x5)) — Figure 21. Typical application with a 32.768 kHz crystal
Figure 21. Typical application with a 32.768 kHz crystal
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32G0B1RBI3N)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32G0B1RBI3N (UFBGA-64(5x5)) is a 64-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.53 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.62 V - 3.6 V supply operation across -40°C to 85°C with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V - 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
55 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-64(5x5))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PA14BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-64(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-64(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32G0B1RBI3N (UFBGA-64(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32G0B1RBI3N (UFBGA-64(5x5))?

Manufactured by ST, the STM32G0B1RBI3N is housed in a UFBGA-64(5x5) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.62 V - 3.6 V. Key pins include: A1 (PC11: Multiplexed I/O & Peripheral Pin PC11 (UART, PWM)), A2 (PC10: Multiplexed I/O & Peripheral Pin PC10 (UART, PWM)), A3 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART, SPI, I2C)), A4 (PB6: Multiplexed I/O & Peripheral Pin PB6 (UART, SPI)), A5 (PD6: Multiplexed I/O & Peripheral Pin PD6 (UART, SPI)), A6 (PD2: Multiplexed I/O & Peripheral Pin PD2 (UART)).

What are the IPC-7351B PCB Footprint dimensions for STM32G0B1RBI3N?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G0B1RBI3N (UFBGA-64(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G0B1RBI3N?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G0B1RBI3N (ST, UFBGA-64(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32G0B1KEU / STM32G0B1RBI Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART, PWM.
A2PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART, PWM.
A3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI, I2C.
A4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, SPI.
A5PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI.
A6PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
A7PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI.
A8PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART, PWM.
B1PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
B2PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
B3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, I2C1_SCLEVEN. Supported peripheral buses: UART, SPI, I2C.
B4PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, I2C.
B5PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI.
B6PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI.
B7PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: USB, UART.
B8PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, USB_DP. Supported peripheral buses: USB, UART, SPI, I2C.
C1PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
C2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
C3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: UART, SPI, I2C, PWM.
C4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, I2C2_SDA. Supported peripheral buses: UART, SPI, I2C.
C5PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
C6PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI_3. Supported peripheral buses: UART, SPI, I2C, RTC/CLK.
C7PA14BOOT0 -Digital_IOSignal terminal PA14BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14BOOT0 -. Supported peripheral buses: UART, SWD/JTAG.
C8PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, USB_DM. Supported peripheral buses: USB, UART, SPI, I2C.
D1VDD/VDDAPower_InPrimary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
D3VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI.
D5PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI.
D6PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, I2C1_SDA. Supported peripheral buses: UART, SPI, I2C.
D7PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: USB, SWD/JTAG.
D8VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E1VSS/VSSAGND0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
E2PF2NRST -Digital_IOSignal terminal PF2NRST - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2NRST -. Supported peripheral buses: UART, RTC/CLK.
E3PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: UART, I2C.
E4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
E5PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
E6PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, I2C, RTC/CLK.
E7PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
E8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F1PF0OSC IN -_Digital_IOSignal terminal PF0OSC IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0OSC IN -_. Supported peripheral buses: RTC/CLK.
F2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: UART, I2C.
F3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI.
F4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, I2C2_SDA. Supported peripheral buses: UART, SPI, I2C, ADC.
F5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI.
F6PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, I2C.
F7PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
F8PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: SPI, I2C, RTC/CLK.
G1PF1 - OSC_OUTDigital_IOSignal terminal PF1 - OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1 - OSC_OUT. Supported peripheral buses: RTC/CLK.
G2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, CAN.
G3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
G4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
G5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, PWM.
G6PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2, I2C2_SCL. Supported peripheral buses: UART, SPI, I2C, ADC.
G7PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI, I2C, ADC.
G8PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C.
H1PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI.
H2PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, ADC.
H3PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, I2C.
H4PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_MOSI, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC.
H5PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART.
H6PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART.
H7PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, RTC/CLK.
H8PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC.
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