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ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-DevKitC-S1

ESPRESSIFID: C571183QFN-48_L6.0-W6.0-P0.40-BL-EP3.8 · 49 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8)1VDDA2LNA_IN3VDD3P34VDD3P35SENSOR_VP6SENSOR_CAPP7SENSOR_CAPN8SENSOR_VN9CHIP_PU10VDET_111VDET_21232K_XP1332K_XN14GPIO2515GPIO2616GPIO2717MTMS18MTDI19VDD3P3_RTC20MTCK21MTDO22GPIO223GPIO024GPIO425GPIO1649GND48CAP147CAP246VDDA45XTAL_P44XTAL_N43VDDA42GPIO2141U0TXD40U0RXD39GPIO2238GPIO1937VDD3P3_CPU36GPIO2335GPIO1834GPIO533SD_DATA1_32SD_DATA0_31SD_CLK30SD_CMD29SD_DATA3_28SD_DATA2_27GPIO1726VDD_SDIOGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=6.00mm · Pitch e=0.40mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
2LNA_INI/OMultiplexed I/O & Peripheral Pin LNA_IN (General)
3VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
4VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
5SENSOR_VPIInput-Only Pin SENSOR_VP (ADC, RTC/CLK)
6SENSOR_CAPPI/OMultiplexed I/O & Peripheral Pin SENSOR_CAPP (ADC, RTC/CLK)
7SENSOR_CAPNI/OMultiplexed I/O & Peripheral Pin SENSOR_CAPN (ADC, RTC/CLK)
8SENSOR_VNIInput-Only Pin SENSOR_VN (ADC, RTC/CLK)
9CHIP_PUISystem Enable & Hardware Reset (CHIP_PU)
10VDET_1I/OMultiplexed I/O & Peripheral Pin VDET_1 (ADC, RTC/CLK)
11VDET_2I/OMultiplexed I/O & Peripheral Pin VDET_2 (ADC, RTC/CLK)
1232K_XPI/OMultiplexed I/O & Peripheral Pin 32K_XP (ADC, RTC/CLK, TOUCH)
1332K_XNI/OMultiplexed I/O & Peripheral Pin 32K_XN (ADC, RTC/CLK, TOUCH)
14GPIO25I/OMultiplexed I/O & Peripheral Pin GPIO25 (UART, ADC, DAC, RTC/CLK)
15GPIO26I/OMultiplexed I/O & Peripheral Pin GPIO26 (UART, ADC, DAC, RTC/CLK)
16GPIO27I/OMultiplexed I/O & Peripheral Pin GPIO27 (ADC, RTC/CLK, TOUCH)
17MTMSI/OMultiplexed I/O & Peripheral Pin MTMS (UART, ADC, SWD/JTAG, RTC/CLK, TOUCH)
18MTDII/OMultiplexed I/O & Peripheral Pin MTDI (UART, ADC, SWD/JTAG, RTC/CLK, TOUCH)
19VDD3P3_RTCPowerPower Supply Input (VDD3P3_RTC — 3.3V VDD3P3 (3.0V ~ 3.6V))
20MTCKI/OMultiplexed I/O & Peripheral Pin MTCK (ADC, SWD/JTAG, RTC/CLK, TOUCH)
21MTDOI/OMultiplexed I/O & Peripheral Pin MTDO (UART, ADC, SWD/JTAG, RTC/CLK, TOUCH)
22GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (ADC, RTC/CLK, TOUCH)
23GPIO0I/OMultiplexed I/O & Peripheral Pin GPIO0 (ADC, RTC/CLK, TOUCH)
24GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (ADC, RTC/CLK, TOUCH)
25GPIO16I/OMultiplexed I/O & Peripheral Pin GPIO16 (General)
26VDD_SDIOPowerPower Supply Input (VDD_SDIO — 3.3V VDD3P3 (3.0V ~ 3.6V))
27GPIO17I/OMultiplexed I/O & Peripheral Pin GPIO17 (General)
28SD_DATA2_I/OMultiplexed I/O & Peripheral Pin SD_DATA2_ (UART, SPI)
29SD_DATA3_I/OMultiplexed I/O & Peripheral Pin SD_DATA3_ (UART, SPI)
30SD_CMDI/OMultiplexed I/O & Peripheral Pin SD_CMD (SPI)
31SD_CLKI/OMultiplexed I/O & Peripheral Pin SD_CLK (SPI)
32SD_DATA0_I/OMultiplexed I/O & Peripheral Pin SD_DATA0_ (SPI)
33SD_DATA1_I/OMultiplexed I/O & Peripheral Pin SD_DATA1_ (SPI)
34GPIO5I/OMultiplexed I/O & Peripheral Pin GPIO5 (General)
35GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
36GPIO23I/OMultiplexed I/O & Peripheral Pin GPIO23 (General)
37VDD3P3_CPUPowerPower Supply Input (VDD3P3_CPU — 3.3V VDD3P3 (3.0V ~ 3.6V))
38GPIO19I/OMultiplexed I/O & Peripheral Pin GPIO19 (UART)
39GPIO22I/OMultiplexed I/O & Peripheral Pin GPIO22 (UART)
40U0RXDI/OMultiplexed I/O & Peripheral Pin U0RXD (UART)
41U0TXDI/OMultiplexed I/O & Peripheral Pin U0TXD (UART)
42GPIO21I/OMultiplexed I/O & Peripheral Pin GPIO21 (General)
43VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
44XTAL_NI/OMultiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
45XTAL_PI/OMultiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
46VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
47CAP2I/OMultiplexed I/O & Peripheral Pin CAP2 (General)
48CAP1I/OMultiplexed I/O & Peripheral Pin CAP1 (General)
49GNDGNDExposed Thermal & Ground Pad (GND)
PIN 1 VDDA
Power
Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
Design note: 模拟电源(23V 36V) . ∼ .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-DevKitC-S1 (ESPRESSIF · QFN-48_L6.0-W6.0-P0.40-BL-EP3.8)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) - 4. Package Dimensions (D×E×A)
QFN-48_L6.0-W6.0-P0.40-BL-EP3.8 · 6.00×6.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for ESP32-DEVKITC
P1 · p01_fig01642×314px
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) — www.espressif.com
www.espressif.com
P13 · p13_fig011312×1180px
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) — 图2: ESP32 管脚布局（封装为QFN 6*6，顶视图）
图2: ESP32 管脚布局（封装为QFN 6*6，顶视图）
P14 · p14_fig011336×1178px
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) — 图3: ESP32 管脚布局（封装为QFN 5*5，顶视图）
图3: ESP32 管脚布局（封装为QFN 5*5，顶视图）
P14 · p14_fig01P14
ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) — Datasheet Page 14 (p14_fig01)
Datasheet Page 14 (p14_fig01)

Technical Specifications & Part Details (ESP32-DevKitC-S1)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) is a 48-pin wireless wi-fi / bluetooth le soc module featuring a 6.00 × 6.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 65 V ~ 2.0 V supply operation across 40 °C ~ 105 °C with integrated Wi-Fi, UART, SPI, I2C, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG, TOUCH interfaces.
Operating Supply VoltageV_CC / V_DD
65 V ~ 2.0 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40 °C ~ 105 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
500 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8)
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, UART, SPI, I2C, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG, TOUCH
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (MTDI, MTDO, GPIO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 3.80×3.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.67 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8)?

Manufactured by ESPRESSIF, the ESP32-DevKitC-S1 is housed in a QFN-48_L6.0-W6.0-P0.40-BL-EP3.8 package with 49 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 65 V ~ 2.0 V. Key pins include: 1 (VDDA: Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))), 2 (LNA_IN: Multiplexed I/O & Peripheral Pin LNA_IN (General)), 3 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 4 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 5 (SENSOR_VP: Input-Only Pin SENSOR_VP (ADC, RTC/CLK)), 6 (SENSOR_CAPP: Multiplexed I/O & Peripheral Pin SENSOR_CAPP (ADC, RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-DevKitC-S1?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-DevKitC-S1 (QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.40 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.80 × 3.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-DevKitC-S1?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-DevKitC-S1 (ESPRESSIF, QFN-48_L6.0-W6.0-P0.40-BL-EP3.8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & ESP32-DEVKITC Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
2LNA_INRF_50OhmSignal terminal LNA_IN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
3VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
4VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
5SENSOR_VPDigital_IOSignal terminal SENSOR_VP (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO36, ADC1_CH0, RTC_GPIO0. Supported peripheral buses: ADC, RTC/CLK.
6SENSOR_CAPPDigital_IOSignal terminal SENSOR_CAPP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO37, ADC1_CH1, RTC_GPIO1. Supported peripheral buses: ADC, RTC/CLK.
7SENSOR_CAPNDigital_IOSignal terminal SENSOR_CAPN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO38, ADC1_CH2, RTC_GPIO2. Supported peripheral buses: ADC, RTC/CLK.
8SENSOR_VNDigital_IOSignal terminal SENSOR_VN (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO39, ADC1_CH3, RTC_GPIO3. Supported peripheral buses: ADC, RTC/CLK.
9CHIP_PUDigital_IOChip enable and power-on reset control input (CHIP_PU): High enables the SoC; Low powers down the chip into reset.
10VDET_1Digital_IOSignal terminal VDET_1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO34, ADC1_CH6, RTC_GPIO4. Supported peripheral buses: ADC, RTC/CLK.
11VDET_2Digital_IOSignal terminal VDET_2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO35, ADC1_CH7, RTC_GPIO5. Supported peripheral buses: ADC, RTC/CLK.
1232K_XPDigital_IOSignal terminal 32K_XP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO32, ADC1_CH4, RTC_GPIO9, TOUCH9. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
1332K_XNDigital_IOSignal terminal 32K_XN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO33, ADC1_CH5, RTC_GPIO8, TOUCH8. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
14GPIO25Digital_IOSignal terminal GPIO25 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ADC2_CH8, RTC_GPIO6. Supported peripheral buses: UART, ADC, DAC, RTC/CLK.
15GPIO26Digital_IOSignal terminal GPIO26 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ADC2_CH9, RTC_GPIO7. Supported peripheral buses: UART, ADC, DAC, RTC/CLK.
16GPIO27Digital_IOSignal terminal GPIO27 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ADC2_CH7, RTC_GPIO17, TOUCH7. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
17MTMSDigital_IOSignal terminal MTMS (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO14, ADC2_CH6, RTC_GPIO16, TOUCH6. Supported peripheral buses: UART, ADC, SWD/JTAG, RTC/CLK, TOUCH.
18MTDIDigital_IOSignal terminal MTDI (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO12, ADC2_CH5, RTC_GPIO15, TOUCH5. Supported peripheral buses: UART, ADC, SWD/JTAG, RTC/CLK, TOUCH.
19VDD3P3_RTCPower_InPrimary positive power supply input (VDD3P3_RTC) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
20MTCKDigital_IOSignal terminal MTCK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO13, ADC2_CH4, RTC_GPIO14, TOUCH4. Supported peripheral buses: ADC, SWD/JTAG, RTC/CLK, TOUCH.
21MTDODigital_IOSignal terminal MTDO (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO15, ADC2_CH3, RTC_GPIO13, TOUCH3. Supported peripheral buses: UART, ADC, SWD/JTAG, RTC/CLK, TOUCH.
22GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ADC2_CH2, RTC_GPIO12, TOUCH2. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
23GPIO0Digital_IOSignal terminal GPIO0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ADC2_CH1, RTC_GPIO11, TOUCH1. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
24GPIO4Digital_IOSignal terminal GPIO4 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ADC2_CH0, RTC_GPIO10, TOUCH0. Supported peripheral buses: ADC, RTC/CLK, TOUCH.
25GPIO16Digital_IOSignal terminal GPIO16 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U2RXD. Supported peripheral buses: General.
26VDD_SDIOPower_InPrimary positive power supply input (VDD_SDIO) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
27GPIO17Digital_IOSignal terminal GPIO17 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U2TXD. Supported peripheral buses: General.
28SD_DATA2_Digital_IOSignal terminal SD_DATA2_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9, U1RXD, SPIHD. Supported peripheral buses: UART, SPI.
29SD_DATA3_Digital_IOSignal terminal SD_DATA3_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO10, U1TXD, SPIWP. Supported peripheral buses: UART, SPI.
30SD_CMDDigital_IOSignal terminal SD_CMD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO11, U1RTS, SPICS0. Supported peripheral buses: SPI.
31SD_CLKDigital_IOSignal terminal SD_CLK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO6, SPICLK. Supported peripheral buses: SPI.
32SD_DATA0_Digital_IOSignal terminal SD_DATA0_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO7, U2RTS, SPIQ. Supported peripheral buses: SPI.
33SD_DATA1_Digital_IOSignal terminal SD_DATA1_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO8, U2CTS, SPID. Supported peripheral buses: SPI.
34GPIO5Digital_IOSignal terminal GPIO5 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO5. Supported peripheral buses: General.
35GPIO18Digital_IOSignal terminal GPIO18 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
36GPIO23Digital_IOSignal terminal GPIO23 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO23. Supported peripheral buses: General.
37VDD3P3_CPUPower_InPrimary positive power supply input (VDD3P3_CPU) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
38GPIO19Digital_IOSignal terminal GPIO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0CTS. Supported peripheral buses: UART.
39GPIO22Digital_IOSignal terminal GPIO22 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RTS. Supported peripheral buses: UART.
40U0RXDDigital_IOSignal terminal U0RXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO3, CLK_OUT2. Supported peripheral buses: UART.
41U0TXDDigital_IOSignal terminal U0TXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO1, CLK_OUT3. Supported peripheral buses: UART.
42GPIO21Digital_IOSignal terminal GPIO21 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO21. Supported peripheral buses: General.
43VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
44XTAL_NDigital_IOSignal terminal XTAL_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
45XTAL_PDigital_IOSignal terminal XTAL_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
46VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
47CAP2Digital_IOSignal terminal CAP2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: CAP2. Supported peripheral buses: General.
48CAP1Digital_IOSignal terminal CAP1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: CAP1. Supported peripheral buses: General.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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