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CH32V467RET6 (LQFP-64(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V467RET6

WCHID: C55471230LQFP-64(7x7) · 64 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V467RET6 (LQFP-64(7x7))1VBAT2PC13/TAMPER-3PC14/OSC32IN4PC15/OSC32OU5OSC_IN/PD06OSC_OUT/PD17NRST8PC0/ADC109PC1/ADC1110PC2/ADC1211PC3/ADC1312VSSA/VREF13VDDA/VREF+14PA0/WKUP/ADC15PA1/ADC116PA2/ADC217PA3/ADC318VDD19PA4/ADC4/DAC20PA5/ADC5/DAC21PA6/ADC622PA7/ADC723PC4/ADC1424PC5/ADC1525PB0/ADC826PB1/ADC927VDDK28MDIRN29MDIRP30MDITN31MDITP32VDD64VDD63VSS62PB961PB860PB759PB658PB557PB456PB355PD254PC1253PC1152PC1051PA1550PA14/SWCLK49VDD48PA13/SWDIO47PA12/USB1DP46PA11/USB1DM45PA1044PA943PA842PD15/LED141PD14/LED040PB1039PB1138PB1537PB1436PB1335PB1234VDD1833VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=7.00mm · Pitch e=0.40mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13/TAMPER-RTCI/OMultiplexed I/O & Peripheral Pin PC13/TAMPER-RTC (RTC/CLK)
3PC14/OSC32INI/OMultiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)
4PC15/OSC32OUTI/OMultiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)
5OSC_IN/PD0I/OMultiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)
6OSC_OUT/PD1I/OMultiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0/ADC10I/OMultiplexed I/O & Peripheral Pin PC0/ADC10 (ADC)
9PC1/ADC11I/OMultiplexed I/O & Peripheral Pin PC1/ADC11 (ADC)
10PC2/ADC12I/OMultiplexed I/O & Peripheral Pin PC2/ADC12 (ADC)
11PC3/ADC13I/OMultiplexed I/O & Peripheral Pin PC3/ADC13 (ADC)
12VSSA/VREFGNDGround Reference Pin (VSSA/VREF)
13VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V / 5.0V Standard Logic)
14PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
15PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
16PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
17PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
18VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
19PA4/ADC4/DAC0I/OMultiplexed I/O & Peripheral Pin PA4/ADC4/DAC0 (ADC, DAC)
20PA5/ADC5/DAC1I/OMultiplexed I/O & Peripheral Pin PA5/ADC5/DAC1 (ADC, DAC)
21PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
22PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
23PC4/ADC14I/OMultiplexed I/O & Peripheral Pin PC4/ADC14 (ADC)
24PC5/ADC15I/OMultiplexed I/O & Peripheral Pin PC5/ADC15 (ADC)
25PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
26PB1/ADC9I/OMultiplexed I/O & Peripheral Pin PB1/ADC9 (ADC)
27VDDKPowerPower Supply Input (VDDK — 3.3V / 5.0V Standard Logic)
28MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
29MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
30MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
31MDITPI/OMultiplexed I/O & Peripheral Pin MDITP (General)
32VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
33VSSGNDGround Reference Pin (VSS)
34VDD18PowerPower Supply Input (VDD18 — 3.3V / 5.0V Standard Logic)
35PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
36PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
37PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
38PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
39PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
40PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
41PD14/LED0I/OMultiplexed I/O & Peripheral Pin PD14/LED0 (General)
42PD15/LED1I/OMultiplexed I/O & Peripheral Pin PD15/LED1 (General)
43PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
44PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
45PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
46PA11/USB1DMI/OMultiplexed I/O & Peripheral Pin PA11/USB1DM (USB)
47PA12/USB1DPI/OMultiplexed I/O & Peripheral Pin PA12/USB1DP (USB)
48PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
49VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
50PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
51PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
52PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
53PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
54PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
55PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
56PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
57PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
58PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
59PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
60PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
61PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
62PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
63VSSGNDGround Reference Pin (VSS)
64VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: VBAT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V467RET6 (WCH · LQFP-64(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V467RET6 (LQFP-64(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V467RET6 (LQFP-64(7x7)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V467RET6 (LQFP-64(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V467RET6 (LQFP-64(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-64(7x7) · 7.00×7.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V467RET6 (LQFP-64(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V467RET6 (LQFP-64(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH32V467
P16 · p16_fig011288×1464px
CH32V467RET6 (LQFP-64(7x7)) — VSS
VSS
P16 · p16_fig021033×1312px
CH32V467RET6 (LQFP-64(7x7)) — 51
51
P16 · p16_fig01P16
CH32V467RET6 (LQFP-64(7x7)) — Datasheet Page 16 (p16_fig01)
Datasheet Page 16 (p16_fig01)
P17 · p17_fig011000×1014px
CH32V467RET6 (LQFP-64(7x7)) — CH32V407、V467 数据手册 https://wch.cn
CH32V407、V467 数据手册 https://wch.cn
P17 · p17_fig021289×1286px
CH32V467RET6 (LQFP-64(7x7)) — V1.2 15
V1.2 15
P43 · p43_fig011438×1088px
CH32V467RET6 (LQFP-64(7x7)) — 图3-1-1 CH32V407 常规供电典型电路
图3-1-1 CH32V407 常规供电典型电路
P43 · p43_fig01P43
CH32V467RET6 (LQFP-64(7x7)) — Datasheet Page 43 (p43_fig01)
Datasheet Page 43 (p43_fig01)
P44 · p44_fig011289×989px
CH32V467RET6 (LQFP-64(7x7)) — 图3-1-2 CH32V467 常规供电典型电路
图3-1-2 CH32V467 常规供电典型电路

Technical Specifications & Part Details (CH32V467RET6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V467RET6 (LQFP-64(7x7)) is a 64-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(7x7))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH32V467 (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (LQFP-64(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V467RET6 (LQFP-64(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V467RET6 (LQFP-64(7x7))?

Manufactured by WCH, the CH32V467RET6 is housed in a LQFP-64(7x7) package with 64 pins and a 0.40 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13/TAMPER-RTC: Multiplexed I/O & Peripheral Pin PC13/TAMPER-RTC (RTC/CLK)), 3 (PC14/OSC32IN: Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)), 4 (PC15/OSC32OUT: Multiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)), 5 (OSC_IN/PD0: Multiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)), 6 (OSC_OUT/PD1: Multiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32V467RET6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V467RET6 (LQFP-64(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.40 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V467RET6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V467RET6 (WCH, LQFP-64(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH32V467 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13/TAMPER-RTCDigital_IOSignal terminal PC13/TAMPER-RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER-RTC. Supported peripheral buses: RTC/CLK.
3PC14/OSC32INDigital_IOSignal terminal PC14/OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK.
4PC15/OSC32OUTDigital_IOSignal terminal PC15/OSC32OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15/OSC32OUT. Supported peripheral buses: RTC/CLK.
5OSC_IN/PD0Digital_IOSignal terminal OSC_IN/PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN/PD0. Supported peripheral buses: RTC/CLK.
6OSC_OUT/PD1Digital_IOSignal terminal OSC_OUT/PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT/PD1. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0/ADC10AnalogSignal terminal PC0/ADC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0/ADC10. Supported peripheral buses: ADC.
9PC1/ADC11AnalogSignal terminal PC1/ADC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1/ADC11. Supported peripheral buses: ADC.
10PC2/ADC12AnalogSignal terminal PC2/ADC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2/ADC12. Supported peripheral buses: ADC.
11PC3/ADC13AnalogSignal terminal PC3/ADC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3/ADC13. Supported peripheral buses: ADC.
12VSSA/VREFGND0V electrical ground return terminal (VSSA/VREF) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
15PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
16PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
17PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
18VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19PA4/ADC4/DAC0AnalogSignal terminal PA4/ADC4/DAC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ADC4/DAC0. Supported peripheral buses: ADC, DAC.
20PA5/ADC5/DAC1AnalogSignal terminal PA5/ADC5/DAC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5/DAC1. Supported peripheral buses: ADC, DAC.
21PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
22PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
23PC4/ADC14AnalogSignal terminal PC4/ADC14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/ADC14. Supported peripheral buses: ADC.
24PC5/ADC15AnalogSignal terminal PC5/ADC15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/ADC15. Supported peripheral buses: ADC.
25PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
26PB1/ADC9AnalogSignal terminal PB1/ADC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC.
27VDDKPower_InPrimary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
29MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
30MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
31MDITPDigital_IOSignal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
33VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
34VDD18Power_InPrimary positive power supply input (VDD18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
35PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
36PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
37PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
38PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
39PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
40PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
41PD14/LED0Digital_IOSignal terminal PD14/LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD14/LED0. Supported peripheral buses: General.
42PD15/LED1Digital_IOSignal terminal PD15/LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD15/LED1. Supported peripheral buses: General.
43PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
44PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
45PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
46PA11/USB1DMDigital_IOSignal terminal PA11/USB1DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/USB1DM. Supported peripheral buses: USB.
47PA12/USB1DPDigital_IOSignal terminal PA12/USB1DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/USB1DP. Supported peripheral buses: USB.
48PA13/SWDIODigital_IOSignal terminal PA13/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG.
49VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
50PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
51PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
52PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
53PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
54PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
55PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
56PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
57PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
58PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
59PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
60PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
61PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
62PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
63VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
64VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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