SOT-23-3L · 3P
Synchronized Pinout (Symbol / 2D / 3D) (3/3)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | DRAIN | Analog | Multiplexed I/O & Peripheral Pin DRAIN (General) |
| 2 | CS | I/O | Multiplexed I/O & Peripheral Pin CS (General) |
| 3 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
PIN 1 DRAIN
AnalogMultiplexed I/O & Peripheral Pin DRAIN (General)
Design note: Signal terminal DRAIN (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRAIN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (3 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
TO-92-2.54mm · 4.80×3.70mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (3 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for KP3110
P2 · p02_fig01EXACT PACKAGE
P2 · p02_fig02EXACT PACKAGE
P7 · p07_fig01EXACT PACKAGE
P1 · p01_fig011836×2013px
P1 · p01_fig01P1
P2 · p02_fig02P2
P7 · p07_fig01P7
P8 · p08_fig01All Packages in PDF
Technical Specifications & Part Details (KP3110LPA)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:KP3110LPA (TO-92-2.54mm) is a 3-pin standard electronic & interconnect component featuring a 4.80 × 3.70 × 4.60 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
31kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.80 × 3.70 × 4.60 mm (A1=1.50 mm)
Package family: TO92 (TO-92-2.54mm)
Pin Count & Lead PitchN / e
3 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol3 auto-grouped pins
IPC-7351B Land Pattern3 pads · Pitch 2.54mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — KP3110 (2)
TO-92-2.54mm · 3P
Mechanical Dimensions & Land Pattern (TO-92-2.54mm)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.80 × 3.70 mm
Height (A) & Pitch (e)IPC-7351B
A=4.60mm · e=2.54mm
Pad Size (W × L)Level B
0.95 × 1.55 mm
Pins / Total PadsTopology
3P / 3Pad (THT_TO92)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TO-92-2.54mm | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — KP3110LPA (TO-92-2.54mm)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of KP3110LPA (TO-92-2.54mm)?
Manufactured by Kiwi Instruments, the KP3110LPA is housed in a TO-92-2.54mm package with 3 pins and a 2.54 mm lead pitch. Key pins include: 1 (DRAIN: Multiplexed I/O & Peripheral Pin DRAIN (General)), 2 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 3 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)).
What are the IPC-7351B PCB Footprint dimensions for KP3110LPA?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KP3110LPA (TO-92-2.54mm) has a nominal body envelope of 3.70 × 4.80 mm, pitch e = 2.54 mm, and 3 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KP3110LPA?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KP3110LPA (Kiwi Instruments, TO-92-2.54mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (3 pins) & KP3110 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | DRAIN | Analog | Signal terminal DRAIN (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRAIN. Supported peripheral buses: General. |
| 2 | CS | Digital_IO | Signal terminal CS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS. Supported peripheral buses: General. |
| 3 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |