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C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) — Symbol, Footprint IPC-7351B & 3D STEP Model

C554025

SemiconductorSOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR · 3 Pins · Pitch 1.90mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR)1DRAIN2VDD3CSGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.210.25.10-5.1-10.2mm
2. 2D FOOTPRINT
123E=2.90mm · Pitch e=1.90mmD=1.30mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.90mm × 1.30mm · Pitch: 1.90mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (3/3)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DRAINI/OMultiplexed I/O & Peripheral Pin DRAIN (General)
2VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
3CSI/OMultiplexed I/O & Peripheral Pin CS (General)
PIN 1 DRAIN
I/O
Multiplexed I/O & Peripheral Pin DRAIN (General)
Design note: Signal terminal DRAIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRAIN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C554025 (Semiconductor · SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) - 2. Standard Pinout (Top View)
True package pinout (3 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) - 4. Package Dimensions (D×E×A)
SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR · 2.90×1.30mm · Pitch 1.90mmExpand ›
5. Recommended Land PatternLAND PATTERN
C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) - 5. Recommended Land Pattern
IPC-7351B Footprint (3 Pads)Expand ›
6. Application SchematicSCHEMATIC
C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C554025)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) is a 3-pin standard electronic & interconnect component featuring a 2.90 × 1.30 × 1.10 mm mechanical envelope (lead pitch e = 1.90 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.90 × 1.30 × 1.10 mm (A1=0.07 mm)
Package family: SOT23 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR)
Pin Count & Lead PitchN / e
3 Pins | Pitch e = 1.90 mm (74.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol3 auto-grouped pins
OK
IPC-7351B Land Pattern3 pads · Pitch 1.90mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.90 × 1.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=1.90mm
Pad Size (W × L)Level B
0.65 × 1.00 mm
Pins / Total PadsTopology
3P / 3Pad (SOT_SMALL)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR)?

Manufactured by Semiconductor, the C554025 is housed in a SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR package with 3 pins and a 1.90 mm lead pitch. Key pins include: 1 (DRAIN: Multiplexed I/O & Peripheral Pin DRAIN (General)), 2 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 3 (CS: Multiplexed I/O & Peripheral Pin CS (General)).

What are the IPC-7351B PCB Footprint dimensions for C554025?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C554025 (SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) has a nominal body envelope of 1.30 × 2.90 mm, pitch e = 1.90 mm, and 3 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C554025?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C554025 (Semiconductor, SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (3 pins) & KP3110 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DRAINDigital_IOSignal terminal DRAIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRAIN. Supported peripheral buses: General.
2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3CSDigital_IOSignal terminal CS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS. Supported peripheral buses: General.
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