ESSOP-10-150mil-1mm · 11P
Synchronized Pinout (Symbol / 2D / 3D) (29/29)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | X32K0 | I/O | Multiplexed I/O & Peripheral Pin X32K0 (General) |
| 2 | X32KI | I/O | Multiplexed I/O & Peripheral Pin X32KI (General) |
| 3 | VDD_D | Power | Power Supply Input (VDD_D — 3.3V / 5.0V Standard Logic) |
| 4 | VSW | I/O | Multiplexed I/O & Peripheral Pin VSW (General) |
| 5 | VCC | Power | Power Supply Input (VCC — 3.3V / 5.0V Standard Logic) |
| 6 | AT | I/O | Multiplexed I/O & Peripheral Pin AT (General) |
| 7 | ADC | I/O | Multiplexed I/O & Peripheral Pin ADC (ADC) |
| 8 | DCD#/GPIO7 | I/O | Multiplexed I/O & Peripheral Pin DCD#/GPIO7 (General) |
| 9 | DSR#/GPIO6 | I/O | Multiplexed I/O & Peripheral Pin DSR#/GPIO6 (UART) |
| 10 | RI#/GPIO5 | I/O | Multiplexed I/O & Peripheral Pin RI#/GPIO5 (General) |
| 11 | DTR#/BLESTA/GPIO4 | I/O | Multiplexed I/O & Peripheral Pin DTR#/BLESTA/GPIO4 (UART) |
| 12 | RTS#/TNOW | I/O | Multiplexed I/O & Peripheral Pin RTS#/TNOW (UART) |
| 13 | CTS | I/O | Multiplexed I/O & Peripheral Pin CTS (UART) |
| 14 | TXD | I/O | Multiplexed I/O & Peripheral Pin TXD (UART) |
| 15 | RXD | I/O | Multiplexed I/O & Peripheral Pin RXD (UART) |
| 16 | RST# | I/O | Multiplexed I/O & Peripheral Pin RST# (General) |
| 17 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 18 | X32MO | I/O | Multiplexed I/O & Peripheral Pin X32MO (General) |
| 19 | X32MI | I/O | Multiplexed I/O & Peripheral Pin X32MI (General) |
| 20 | VINTA | Power | Power Supply Input (VINTA — 3.3V / 5.0V Standard Logic) |
| 21 | ANT | I/O | Multiplexed I/O & Peripheral Pin ANT (General) |
| 22 | VDD_A | Power | Power Supply Input (VDD_A — 3.3V / 5.0V Standard Logic) |
| 23 | RELOAD/LED | I/O | Multiplexed I/O & Peripheral Pin RELOAD/LED (General) |
| 24 | SLEEP | I/O | Multiplexed I/O & Peripheral Pin SLEEP (General) |
| 25 | GPIO3 | I/O | Multiplexed I/O & Peripheral Pin GPIO3 (General) |
| 26 | GPIO2 | I/O | Multiplexed I/O & Peripheral Pin GPIO2 (General) |
| 27 | GPIO1 | I/O | Multiplexed I/O & Peripheral Pin GPIO1 (General) |
| 28 | GPIO0 | I/O | Multiplexed I/O & Peripheral Pin GPIO0 (General) |
| 29 | GND | GND | Ground Reference Pin (GND) |
PIN 1 X32K0
I/OMultiplexed I/O & Peripheral Pin X32K0 (General)
Design note: Signal terminal X32K0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32K0. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-28(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH9141
P2 · p02_fig03EXACT PACKAGE
P1 · p01_fig011505×397px
P1 · p01_fig02997×346px
P1 · p01_fig03994×347px
P2 · p02_fig01722×690px
P2 · p02_fig02649×381px
P2 · p02_fig01P2
P2 · p02_fig02P2
P2 · p02_fig03P2
P8 · p08_fig011745×2509px
Technical Specifications & Part Details (CH9141F)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH9141F (QFN-28(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, UART, ADC interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, UART, ADC
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (GPIO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol29 auto-grouped pins
IPC-7351B Land Pattern29 pads · Pitch 0.40mm
IPC-7525 60% Solder PasteEPAD 2.60×2.60mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH9141 (3)
QFN-28(4x4) · 29P
QFN-28-EP(4x4) · 29P
Mechanical Dimensions & Land Pattern (QFN-28(4x4))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-28(4x4) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH9141F (QFN-28(4x4))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH9141F (QFN-28(4x4))?
Manufactured by WCH, the CH9141F is housed in a QFN-28(4x4) package with 29 pins and a 0.40 mm lead pitch. Key pins include: 1 (X32K0: Multiplexed I/O & Peripheral Pin X32K0 (General)), 2 (X32KI: Multiplexed I/O & Peripheral Pin X32KI (General)), 3 (VDD_D: Power Supply Input (VDD_D — 3.3V / 5.0V Standard Logic)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 5 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 6 (AT: Multiplexed I/O & Peripheral Pin AT (General)).
What are the IPC-7351B PCB Footprint dimensions for CH9141F?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9141F (QFN-28(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.60 × 2.60 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9141F?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9141F (WCH, QFN-28(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (29 pins) & CH9141 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | X32K0 | Digital_IO | Signal terminal X32K0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32K0. Supported peripheral buses: General. |
| 2 | X32KI | Digital_IO | Signal terminal X32KI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KI. Supported peripheral buses: General. |
| 3 | VDD_D | Power_In | Primary positive power supply input (VDD_D) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 4 | VSW | Digital_IO | Signal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General. |
| 5 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 6 | AT | Digital_IO | Signal terminal AT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AT. Supported peripheral buses: General. |
| 7 | ADC | Analog | Signal terminal ADC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADC. Supported peripheral buses: ADC. |
| 8 | DCD#/GPIO7 | Digital_IO | Signal terminal DCD#/GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD#/GPIO7. Supported peripheral buses: General. |
| 9 | DSR#/GPIO6 | Digital_IO | Signal terminal DSR#/GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR#/GPIO6. Supported peripheral buses: UART. |
| 10 | RI#/GPIO5 | Digital_IO | Signal terminal RI#/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI#/GPIO5. Supported peripheral buses: General. |
| 11 | DTR#/BLESTA/GPIO4 | Digital_IO | Signal terminal DTR#/BLESTA/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR#/BLESTA/GPIO4. Supported peripheral buses: UART. |
| 12 | RTS#/TNOW | Digital_IO | Signal terminal RTS#/TNOW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS#/TNOW. Supported peripheral buses: UART. |
| 13 | CTS | Digital_IO | Signal terminal CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART. |
| 14 | TXD | Digital_IO | Signal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART. |
| 15 | RXD | Digital_IO | Signal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART. |
| 16 | RST# | Digital_IO | Signal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General. |
| 17 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 18 | X32MO | Digital_IO | Signal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General. |
| 19 | X32MI | Digital_IO | Signal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General. |
| 20 | VINTA | Power_In | Primary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 21 | ANT | RF_50Ohm | Signal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General. |
| 22 | VDD_A | Power_In | Primary positive power supply input (VDD_A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 23 | RELOAD/LED | Digital_IO | Signal terminal RELOAD/LED (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RELOAD/LED. Supported peripheral buses: General. |
| 24 | SLEEP | Digital_IO | Signal terminal SLEEP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLEEP. Supported peripheral buses: General. |
| 25 | GPIO3 | Digital_IO | Signal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General. |
| 26 | GPIO2 | Digital_IO | Signal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General. |
| 27 | GPIO1 | Digital_IO | Signal terminal GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General. |
| 28 | GPIO0 | Digital_IO | Signal terminal GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General. |
| 29 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |