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CH398X5 (QFN-40E(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH398X5

WCHID: C55013891QFN-40E(5x5) · 41 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH398X5 (QFN-40E(5x5))1MDI0P2ETH3AVDDK4ETH5ETH6MDI2P7MDI2N8AVDDK9MDI3P10MDI3N11AVDD3312USB313USB314P P15USB316USB317USB218USB219DVDDK20P P21NC41GND40P P39P P38P P37AVDDK36XO35XI34P P33VDD3332LED031NC30LED129P28P27VDD526P25SUSP#/CFG24LED223NC22P PGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.233.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041E=5.00mm · Pitch e=0.40mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (41/41)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MDI0PI/OMultiplexed I/O & Peripheral Pin MDI0P (General)
2ETHI/OMultiplexed I/O & Peripheral Pin ETH (General)
3AVDDKPowerPower Supply Input (AVDDK — 3.3V / 5.0V Standard Logic)
4ETHI/OMultiplexed I/O & Peripheral Pin ETH (General)
5ETHI/OMultiplexed I/O & Peripheral Pin ETH (General)
6MDI2PI/OMultiplexed I/O & Peripheral Pin MDI2P (General)
7MDI2NI/OMultiplexed I/O & Peripheral Pin MDI2N (General)
8AVDDKPowerPower Supply Input (AVDDK — 3.3V / 5.0V Standard Logic)
9MDI3PI/OMultiplexed I/O & Peripheral Pin MDI3P (General)
10MDI3NI/OMultiplexed I/O & Peripheral Pin MDI3N (General)
11AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
12USB3I/OMultiplexed I/O & Peripheral Pin USB3 (USB)
13USB3I/OMultiplexed I/O & Peripheral Pin USB3 (USB)
14P PI/OMultiplexed I/O & Peripheral Pin P P (General)
15USB3I/OMultiplexed I/O & Peripheral Pin USB3 (USB)
16USB3I/OMultiplexed I/O & Peripheral Pin USB3 (USB)
17USB2I/OMultiplexed I/O & Peripheral Pin USB2 (USB)
18USB2I/OMultiplexed I/O & Peripheral Pin USB2 (USB)
19DVDDKPowerPower Supply Input (DVDDK — 3.3V / 5.0V Standard Logic)
20P PI/OMultiplexed I/O & Peripheral Pin P P (General)
21NCI/OMultiplexed I/O & Peripheral Pin NC (General)
22P PI/OMultiplexed I/O & Peripheral Pin P P (General)
23NCI/OMultiplexed I/O & Peripheral Pin NC (General)
24LED2I/OMultiplexed I/O & Peripheral Pin LED2 (General)
25SUSP#/CFGI/OMultiplexed I/O & Peripheral Pin SUSP#/CFG (General)
26PI/OMultiplexed I/O & Peripheral Pin P (General)
27VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
28PI/OMultiplexed I/O & Peripheral Pin P (General)
29PI/OMultiplexed I/O & Peripheral Pin P (General)
30LED1I/OMultiplexed I/O & Peripheral Pin LED1 (General)
31NCI/OMultiplexed I/O & Peripheral Pin NC (General)
32LED0I/OMultiplexed I/O & Peripheral Pin LED0 (General)
33VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
34P PI/OMultiplexed I/O & Peripheral Pin P P (General)
35XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
36XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
37AVDDKPowerPower Supply Input (AVDDK — 3.3V / 5.0V Standard Logic)
38P PI/OMultiplexed I/O & Peripheral Pin P P (General)
39P PI/OMultiplexed I/O & Peripheral Pin P P (General)
40P PI/OMultiplexed I/O & Peripheral Pin P P (General)
41GNDGNDGround Reference Pin (GND)
PIN 1 MDI0P
I/O
Multiplexed I/O & Peripheral Pin MDI0P (General)
Design note: Signal terminal MDI0P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDI0P. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH398X5 (WCH · QFN-40E(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH398X5 (QFN-40E(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH398X5 (QFN-40E(5x5)) - 2. Standard Pinout (Top View)
True package pinout (41 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH398X5 (QFN-40E(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH398X5 (QFN-40E(5x5)) - 4. Package Dimensions (D×E×A)
QFN-40E(5x5) · 5.00×5.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH398X5 (QFN-40E(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (41 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH398X5 (QFN-40E(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH398
P2 · p02_fig01EXACT PACKAGE
CH398X5 (QFN-40E(5x5)) — 4、引脚定义
4、引脚定义
P2 · p02_fig02EXACT PACKAGE
CH398X5 (QFN-40E(5x5)) — V1.4 2
V1.4 2
P6 · p06_fig011723×1131px
CH398X5 (QFN-40E(5x5)) — 注：VDD33、AVDD33、AVDDK 以及DVDDK 在芯片封装中有多个引脚，同名电源引脚短接，VDD33 与AVDD33
注：VDD33、AVDD33、AVDDK 以及DVDDK 在芯片封装中有多个引脚，同名电源引脚短接，VDD33 与AVDD33
P8 · p08_fig011707×1058px
CH398X5 (QFN-40E(5x5)) — 图5-2-3 单一3.3V 非DCDC 供电方案示意图
图5-2-3 单一3.3V 非DCDC 供电方案示意图
P14 · p14_fig011613×2017px
CH398X5 (QFN-40E(5x5)) — 图8-1 USB 以太网桥接芯片CH398X 应用参考 VDD5
图8-1 USB 以太网桥接芯片CH398X 应用参考 VDD5
P14 · p14_fig01P14
CH398X5 (QFN-40E(5x5)) — Datasheet Page 14 (p14_fig01)
Datasheet Page 14 (p14_fig01)

Technical Specifications & Part Details (CH398X5)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH398X5 (QFN-40E(5x5)) is a 40-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-40E(5x5))
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol41 auto-grouped pins
OK
IPC-7351B Land Pattern41 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-40E(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
41P / 41Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-40E(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH398X5 (QFN-40E(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH398X5 (QFN-40E(5x5))?

Manufactured by WCH, the CH398X5 is housed in a QFN-40E(5x5) package with 41 pins and a 0.40 mm lead pitch. Key pins include: 1 (MDI0P: Multiplexed I/O & Peripheral Pin MDI0P (General)), 2 (ETH: Multiplexed I/O & Peripheral Pin ETH (General)), 3 (AVDDK: Power Supply Input (AVDDK — 3.3V / 5.0V Standard Logic)), 4 (ETH: Multiplexed I/O & Peripheral Pin ETH (General)), 5 (ETH: Multiplexed I/O & Peripheral Pin ETH (General)), 6 (MDI2P: Multiplexed I/O & Peripheral Pin MDI2P (General)).

What are the IPC-7351B PCB Footprint dimensions for CH398X5?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH398X5 (QFN-40E(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.40 mm, and 41 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH398X5?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH398X5 (WCH, QFN-40E(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (41 pins) & CH398 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MDI0PDigital_IOSignal terminal MDI0P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDI0P. Supported peripheral buses: General.
2ETHDigital_IOSignal terminal ETH (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ETH. Supported peripheral buses: General.
3AVDDKPower_InPrimary positive power supply input (AVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4ETHDigital_IOSignal terminal ETH (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ETH. Supported peripheral buses: General.
5ETHDigital_IOSignal terminal ETH (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ETH. Supported peripheral buses: General.
6MDI2PDigital_IOSignal terminal MDI2P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDI2P. Supported peripheral buses: General.
7MDI2NDigital_IOSignal terminal MDI2N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDI2N. Supported peripheral buses: General.
8AVDDKPower_InPrimary positive power supply input (AVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9MDI3PDigital_IOSignal terminal MDI3P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDI3P. Supported peripheral buses: General.
10MDI3NDigital_IOSignal terminal MDI3N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDI3N. Supported peripheral buses: General.
11AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12USB3Digital_IOSignal terminal USB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3. Supported peripheral buses: USB.
13USB3Digital_IOSignal terminal USB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3. Supported peripheral buses: USB.
14P PDigital_IOSignal terminal P P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P P. Supported peripheral buses: General.
15USB3Digital_IOSignal terminal USB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3. Supported peripheral buses: USB.
16USB3Digital_IOSignal terminal USB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3. Supported peripheral buses: USB.
17USB2Digital_IOSignal terminal USB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2. Supported peripheral buses: USB.
18USB2Digital_IOSignal terminal USB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB2. Supported peripheral buses: USB.
19DVDDKPower_InPrimary positive power supply input (DVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20P PDigital_IOSignal terminal P P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P P. Supported peripheral buses: General.
21NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
22P PDigital_IOSignal terminal P P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P P. Supported peripheral buses: General.
23NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
24LED2Digital_IOSignal terminal LED2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED2. Supported peripheral buses: General.
25SUSP#/CFGDigital_IOSignal terminal SUSP#/CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSP#/CFG. Supported peripheral buses: General.
26PDigital_IOSignal terminal P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P. Supported peripheral buses: General.
27VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28PDigital_IOSignal terminal P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P. Supported peripheral buses: General.
29PDigital_IOSignal terminal P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P. Supported peripheral buses: General.
30LED1Digital_IOSignal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General.
31NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
32LED0Digital_IOSignal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General.
33VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34P PDigital_IOSignal terminal P P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P P. Supported peripheral buses: General.
35XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
36XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
37AVDDKPower_InPrimary positive power supply input (AVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
38P PDigital_IOSignal terminal P P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P P. Supported peripheral buses: General.
39P PDigital_IOSignal terminal P P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P P. Supported peripheral buses: General.
40P PDigital_IOSignal terminal P P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P P. Supported peripheral buses: General.
41GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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