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CH275J (QFN-14F(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH275J

WCHID: C55013890QFN-14F(3x3) · 14 Pins · Pitch 0.50mmDISCREPANCY REVIEW REQUIRED5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH275J (QFN-14F(3x3))1VDD52AI3AO4PWM15PWM26BS27SW214VDD3313GND12SW111VHV10VHV9CSO8BS1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.215.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
1356711109812144321E=3.00mm · Pitch e=0.50mmD=3.00mm-4-3-2-1012343210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (14/14)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
2AII/OMultiplexed I/O & Peripheral Pin AI (General)
3AOI/OMultiplexed I/O & Peripheral Pin AO (General)
4PWM1I/OMultiplexed I/O & Peripheral Pin PWM1 (PWM)
5PWM2I/OMultiplexed I/O & Peripheral Pin PWM2 (PWM)
6BS2I/OMultiplexed I/O & Peripheral Pin BS2 (General)
7SW2I/OMultiplexed I/O & Peripheral Pin SW2 (PWM)
8BS1I/OMultiplexed I/O & Peripheral Pin BS1 (General)
9CSOI/OMultiplexed I/O & Peripheral Pin CSO (General)
10VHVI/OMultiplexed I/O & Peripheral Pin VHV (General)
11VHVI/OMultiplexed I/O & Peripheral Pin VHV (General)
12SW1I/OMultiplexed I/O & Peripheral Pin SW1 (PWM)
13GNDGNDGround Reference Pin (GND)
14VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
PIN 1 VDD5
Power
Power Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
Design note: 内部5V电压稳压器LDO输出 ， 紧贴引脚外接至少1uF 电容 ，建议2 .2uF 以上
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH275J (WCH · QFN-14F(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH275J (QFN-14F(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH275J (QFN-14F(3x3)) - 2. Standard Pinout (Top View)
True package pinout (14 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH275J (QFN-14F(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH275J (QFN-14F(3x3)) - 4. Package Dimensions (D×E×A)
QFN-14F(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH275J (QFN-14F(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (14 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH275J (QFN-14F(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH275
P8 · p08_fig02EXACT PACKAGE
CH275J (QFN-14F(3x3)) — 8.1. QFN14F_3x3x0.55-0.5
8.1. QFN14F_3x3x0.55-0.5
P1 · p01_fig011697×1640px
CH275J (QFN-14F(3x3)) — 下面为CH275 的内部框图，仅供参考。
下面为CH275 的内部框图，仅供参考。
P2 · p02_fig011790×1209px
CH275J (QFN-14F(3x3)) — PWM2 5 GND 13 VDD33 14 | VHV 11 VHV 10 CSO 9 | SW1 12 | BS1 8 AI 2 VDD5 1 | SW2 7 | PWM1 4 | BS2 6 | AO 3 | CH275J | PWM2 5 GND 13 VDD33 14 | VHV 11 VHV 10 PWME 9 | SW1 12 | BS1 8 AI 2 VDD5 1 | SW2 7 | PWM1 4 | BS2 6 | AO 3 | CH275P | 3、引脚排
PWM2 5 GND 13 VDD33 14 | VHV 11 VHV 10 CSO 9 | SW1 12 | BS1 8 AI 2 VDD5 1 | SW2 7 | PWM1 4 | BS2 6 | AO 3 | CH275J | PWM2 5 GND 13 VDD33 14 | VHV 11 VHV 10 PWME 9 | SW1 12 | BS1 8 AI 2 VDD5 1 | SW2 7 | PWM1 4 | BS2 6 | AO 3 | CH275P | 3、引脚排
P2 · p02_fig01P2
CH275J (QFN-14F(3x3)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P5 · p05_fig011728×1923px
CH275J (QFN-14F(3x3)) — 版本：1.3 ５
版本：1.3 ５
P7 · p07_fig012018×1589px
CH275J (QFN-14F(3x3)) — 版本：1.3 ７
版本：1.3 ７
P8 · p08_fig011866×800px
CH275J (QFN-14F(3x3)) — 8、封装信息
8、封装信息
P8 · p08_fig01P8
CH275J (QFN-14F(3x3)) — Datasheet Page 8 (p08_fig01)
Datasheet Page 8 (p08_fig01)

Technical Specifications & Part Details (CH275J)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH275J (QFN-14F(3x3)) is a 14-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-14F(3x3))
Pin Count & Lead PitchN / e
14 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BS2, BS1): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol14 auto-grouped pins
OK
IPC-7351B Land Pattern14 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-14F(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.50 mm
Pins / Total PadsTopology
14P / 14Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-14F(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH275J (QFN-14F(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH275J (QFN-14F(3x3))?

Manufactured by WCH, the CH275J is housed in a QFN-14F(3x3) package with 14 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD5: Power Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)), 2 (AI: Multiplexed I/O & Peripheral Pin AI (General)), 3 (AO: Multiplexed I/O & Peripheral Pin AO (General)), 4 (PWM1: Multiplexed I/O & Peripheral Pin PWM1 (PWM)), 5 (PWM2: Multiplexed I/O & Peripheral Pin PWM2 (PWM)), 6 (BS2: Multiplexed I/O & Peripheral Pin BS2 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH275J?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH275J (QFN-14F(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 14 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH275J?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH275J (WCH, QFN-14F(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (14 pins) & CH275 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2AIDigital_IOSignal terminal AI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AI. Supported peripheral buses: General.
3AODigital_IOSignal terminal AO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AO. Supported peripheral buses: General.
4PWM1Digital_IOSignal terminal PWM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM1. Supported peripheral buses: PWM.
5PWM2Digital_IOSignal terminal PWM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM2. Supported peripheral buses: PWM.
6BS2Digital_IOSignal terminal BS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BS2. Supported peripheral buses: General.
7SW2Digital_IOSignal terminal SW2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SW2. Supported peripheral buses: PWM.
8BS1Digital_IOSignal terminal BS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BS1. Supported peripheral buses: General.
9CSODigital_IOSignal terminal CSO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CSO. Supported peripheral buses: General.
10VHVDigital_IOSignal terminal VHV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VHV. Supported peripheral buses: General.
11VHVDigital_IOSignal terminal VHV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VHV. Supported peripheral buses: General.
12SW1Digital_IOSignal terminal SW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SW1. Supported peripheral buses: PWM.
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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