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CH596D (QFN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH596D

WCHID: C54973464QFN-20(3x3) · 21 Pins · Pitch 0.50mmDISCREPANCY REVIEW REQUIRED5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH596D (QFN-20(3x3))1PA102PB6/PWM8/A93VIO15/VDD154PA8/RXD1/A125PA9/TMR0/TXD6PB15/MISO_/S7PB14/MOSI_/S8PB13/SCK0_/T9PB1210PB1111PB1021GND20PA1119PA1218PA1317PA1416PA1515ANT14VINTA13X32MI12X32MOGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.50mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (ADC)
2PB6/PWM8/A9I/OMultiplexed I/O & Peripheral Pin PB6/PWM8/A9 (PWM)
3VIO15/VDD15PowerPower Supply Input (VIO15/VDD15 — 3.3V / 5.0V Standard Logic)
4PA8/RXD1/A12I/OMultiplexed I/O & Peripheral Pin PA8/RXD1/A12 (UART)
5PA9/TMR0/TXD1/A13I/OMultiplexed I/O & Peripheral Pin PA9/TMR0/TXD1/A13 (UART)
6PB15/MISO_/SCLI/OMultiplexed I/O & Peripheral Pin PB15/MISO_/SCL (SPI, I2C)
7PB14/MOSI_/SDA/PWM10I/OMultiplexed I/O & Peripheral Pin PB14/MOSI_/SDA/PWM10 (SPI, I2C, PWM)
8PB13/SCK0_/TXD1I/OMultiplexed I/O & Peripheral Pin PB13/SCK0_/TXD1 (UART, SPI)
9PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART)
10PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
11PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
12X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
13X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
14VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
15ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
16PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, ADC)
17PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, SPI, ADC)
18PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SPI, ADC, PWM, SWD/JTAG)
19PA12I/OMultiplexed I/O & Peripheral Pin PA12 (PWM)
20PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
21GNDGNDGround Reference Pin (GND)
PIN 1 PA10
I/O
Multiplexed I/O & Peripheral Pin PA10 (ADC)
Design note: X32KI/TMR1 /ENCCAP_IN1_ /AIN6
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH596D (WCH · QFN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH596D (QFN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH596D (QFN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH596D (QFN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH596D (QFN-20(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH596D (QFN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH596D (QFN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH596
P2 · p02_fig01EXACT PACKAGE
CH596D (QFN-20(3x3)) — 支持最低1.2V 电源电压，适用于单节小型电池供电的应用场景。 | 芯片 型号 | 用户闪存 +引导闪存 | 数据 存储 | RAM | RTC | 时 钟 | 定 时 器 | 捕 捉PWM 串 | 口SPI I2C | BLE | 蓝 牙 | ADC | 电容 触摸 按键 | 最低 电源 电压 | 通 用 I/O | 封装 形式 | CH596D 240+16K 24+8K √ 3 3 3+4 2 √ √ √ 8 8 路 1.2V 15 QFN20
支持最低1.2V 电源电压，适用于单节小型电池供电的应用场景。 | 芯片 型号 | 用户闪存 +引导闪存 | 数据 存储 | RAM | RTC | 时 钟 | 定 时 器 | 捕 捉PWM 串 | 口SPI I2C | BLE | 蓝 牙 | ADC | 电容 触摸 按键 | 最低 电源 电压 | 通 用 I/O | 封装 形式 | CH596D 240+16K 24+8K √ 3 3 3+4 2 √ √ √ 8 8 路 1.2V 15 QFN20
P1 · p01_fig01247×133px
CH596D (QFN-20(3x3)) — 概述
概述
P3 · p03_fig011372×1204px
CH596D (QFN-20(3x3)) — CH596 数据手册 https://wch.cn
CH596 数据手册 https://wch.cn
P3 · p03_fig01P3
CH596D (QFN-20(3x3)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011645×2436px
CH596D (QFN-20(3x3)) — V1.1 2
V1.1 2
P4 · p04_fig01P4
CH596D (QFN-20(3x3)) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)
P97 · p97_fig011708×660px
CH596D (QFN-20(3x3)) — CH596 数据手册 https://wch.cn
CH596 数据手册 https://wch.cn
P97 · p97_fig021738×1382px
CH596D (QFN-20(3x3)) — 最大上升时间域。这个位设置主模式的SCL 的上 升时间。最大的上升沿时间等于TRISE-1 个时钟 周期。此位只能在PE 清零下设置。
最大上升时间域。这个位设置主模式的SCL 的上 升时间。最大的上升沿时间等于TRISE-1 个时钟 周期。此位只能在PE 清零下设置。
P98 · p98_fig011713×1889px
CH596D (QFN-20(3x3)) — V1.1 96
V1.1 96

Technical Specifications & Part Details (CH596D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH596D (QFN-20(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, SPI, I2C, ADC, PWM, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, SPI, I2C, ADC, PWM, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 1.90×1.90mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH596D (QFN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH596D (QFN-20(3x3))?

Manufactured by WCH, the CH596D is housed in a QFN-20(3x3) package with 21 pins and a 0.50 mm lead pitch. Key pins include: 1 (PA10: Multiplexed I/O & Peripheral Pin PA10 (ADC)), 2 (PB6/PWM8/A9: Multiplexed I/O & Peripheral Pin PB6/PWM8/A9 (PWM)), 3 (VIO15/VDD15: Power Supply Input (VIO15/VDD15 — 3.3V / 5.0V Standard Logic)), 4 (PA8/RXD1/A12: Multiplexed I/O & Peripheral Pin PA8/RXD1/A12 (UART)), 5 (PA9/TMR0/TXD1/A13: Multiplexed I/O & Peripheral Pin PA9/TMR0/TXD1/A13 (UART)), 6 (PB15/MISO_/SCL: Multiplexed I/O & Peripheral Pin PB15/MISO_/SCL (SPI, I2C)).

What are the IPC-7351B PCB Footprint dimensions for CH596D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH596D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.90 × 1.90 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH596D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH596D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH596 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: ADC.
2PB6/PWM8/A9Digital_IOSignal terminal PB6/PWM8/A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/PWM8/A9. Supported peripheral buses: PWM.
3VIO15/VDD15Power_InPrimary positive power supply input (VIO15/VDD15) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4PA8/RXD1/A12Digital_IOSignal terminal PA8/RXD1/A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8/RXD1/A12. Supported peripheral buses: UART.
5PA9/TMR0/TXD1/A13Digital_IOSignal terminal PA9/TMR0/TXD1/A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9/TMR0/TXD1/A13. Supported peripheral buses: UART.
6PB15/MISO_/SCLDigital_IOSignal terminal PB15/MISO_/SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, I2C.
7PB14/MOSI_/SDA/PWM10Digital_IOSignal terminal PB14/MOSI_/SDA/PWM10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, I2C, PWM.
8PB13/SCK0_/TXD1Digital_IOSignal terminal PB13/SCK0_/TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI.
9PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: UART.
10PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
11PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
12X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
13X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
14VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
16PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: UART, SPI, ADC.
17PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SPI, ADC.
18PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SPI, ADC, PWM, SWD/JTAG.
19PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: PWM.
20PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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