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CH443L (DFN-6(1.2x1.2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH443L

WCHID: C54973458DFN-6(1.2x1.2) · 7 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH443L (DFN-6(1.2x1.2))1IN2S1A S1B 、 、 3S2A S2B 、 、 4DA DB 、 、 DC7DA DB 、 、 DC6S2A S2B 、 、 5S1A S1B 、 、 Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.210.25.10-5.1-10.2mm
2. 2D FOOTPRINT
1234567E=1.20mm · Pitch e=0.40mmD=1.20mm-2-10123210-1-2mm
3. 3D CAD MODEL
Package Body: 1.20mm × 1.20mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (7/7)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1INI/OMultiplexed I/O & Peripheral Pin IN (General)
2S1A S1B 、 、 S1C S1D 、I/OMultiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General)
3S2A S2B 、 、 S2C S2D 、I/OMultiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General)
4DA DB 、 、 DC DD 、I/OMultiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General)
5S1A S1B 、 、 S1C S1D 、I/OMultiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General)
6S2A S2B 、 、 S2C S2D 、I/OMultiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General)
7DA DB 、 、 DC DD 、I/OMultiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General)
PIN 1 IN
I/O
Multiplexed I/O & Peripheral Pin IN (General)
Design note: 二选 一模拟开关选择输入 ： 高电平选择2#端（S2x） ；低电平选择1#端（S1x）
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH443L (WCH · DFN-6(1.2x1.2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH443L (DFN-6(1.2x1.2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH443L (DFN-6(1.2x1.2)) - 2. Standard Pinout (Top View)
True package pinout (7 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH443L (DFN-6(1.2x1.2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH443L (DFN-6(1.2x1.2)) - 4. Package Dimensions (D×E×A)
DFN-6(1.2x1.2) · 1.20×1.20mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH443L (DFN-6(1.2x1.2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (7 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH443L (DFN-6(1.2x1.2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH445 / CH448 / CH440
P2 · p02_fig011491×1615px
CH443L (DFN-6(1.2x1.2)) — 3、引脚排列
3、引脚排列
P2 · p02_fig01P2
CH443L (DFN-6(1.2x1.2)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011729×2206px
CH443L (DFN-6(1.2x1.2)) — 2、QFN 或DFN 封装的底板标示为0#引脚，对于CH448F 是必要连接。 3、CH442Q 与CH9442Q 引脚兼容，CH9442Q 支持Type-C 充电口USB 信号，耐压28V。 4、原型号CH440E 已用新型号CH442E 代替，引脚和功能相同。 5、CH340K 为盘装，每盘整包装数量为3000 只。 6、CH442Q、CH340K、CH443L 封装体积较小，正面印字仅有代号42、43、43 而不含全部型号。 | 4、引脚定义 | 4.1. CH340G
2、QFN 或DFN 封装的底板标示为0#引脚，对于CH448F 是必要连接。 3、CH442Q 与CH9442Q 引脚兼容，CH9442Q 支持Type-C 充电口USB 信号，耐压28V。 4、原型号CH440E 已用新型号CH442E 代替，引脚和功能相同。 5、CH340K 为盘装，每盘整包装数量为3000 只。 6、CH442Q、CH340K、CH443L 封装体积较小，正面印字仅有代号42、43、43 而不含全部型号。 | 4、引脚定义 | 4.1. CH340G
P9 · p09_fig011725×2761px
CH443L (DFN-6(1.2x1.2)) — CH440/CH442/CH443/CH444/CH445/CH448 手册 ９ | 6.3. 额定5V 芯片电气参数@3.3V（测试条件：TA=25℃，VCC=VDD=3.3V，不含CH445） | 6.4. 额定5V 芯片模拟开关时序参数（测试条件：TA=25℃，VCC=VDD=5V，VANA=0V，不含CH445） | 名称 参数说明 最小值 典型值 最大值 单位 CIN 数字输入引脚电容，F=1MHz 4 8 pF | COFF CH448 开关关闭时模拟信号引脚电容
CH440/CH442/CH443/CH444/CH445/CH448 手册 ９ | 6.3. 额定5V 芯片电气参数@3.3V（测试条件：TA=25℃，VCC=VDD=3.3V，不含CH445） | 6.4. 额定5V 芯片模拟开关时序参数（测试条件：TA=25℃，VCC=VDD=5V，VANA=0V，不含CH445） | 名称 参数说明 最小值 典型值 最大值 单位 CIN 数字输入引脚电容，F=1MHz 4 8 pF | COFF CH448 开关关闭时模拟信号引脚电容
P9 · p09_fig01P9
CH443L (DFN-6(1.2x1.2)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P10 · p10_fig011704×2198px
CH443L (DFN-6(1.2x1.2)) — 6.5. 额定3.3V 芯片电气参数@3.3V（测试条件：TA=25℃，VCC=3.3V，仅CH445）
6.5. 额定3.3V 芯片电气参数@3.3V（测试条件：TA=25℃，VCC=3.3V，仅CH445）
P11 · p11_fig011506×749px
CH443L (DFN-6(1.2x1.2)) — VCOM(V) 6.8.2 CH445 的模拟开关导通电阻RON 与模拟信号电压VCOM 的相关性（TA=25℃） RON (Ω)
VCOM(V) 6.8.2 CH445 的模拟开关导通电阻RON 与模拟信号电压VCOM 的相关性（TA=25℃） RON (Ω)
P11 · p11_fig021543×684px
CH443L (DFN-6(1.2x1.2)) — VCOM(V)
VCOM(V)
P17 · p17_fig011210×1387px
CH443L (DFN-6(1.2x1.2)) — D 6 =a] 7 1 a a TEE.
D 6 =a] 7 1 a a TEE.
P17 · p17_fig01P17
CH443L (DFN-6(1.2x1.2)) — Datasheet Page 17 (p17_fig01)
Datasheet Page 17 (p17_fig01)

Technical Specifications & Part Details (CH443L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH443L (DFN-6(1.2x1.2)) is a 6-pin standard electronic & interconnect component featuring a 1.20 × 1.20 × 1.00 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
550 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
1.20 × 1.20 × 1.00 mm (A1=0.03 mm)
Package family: DFN (DFN-6(1.2x1.2))
Pin Count & Lead PitchN / e
6 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol7 auto-grouped pins
OK
IPC-7351B Land Pattern7 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (DFN-6(1.2x1.2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
1.20 × 1.20 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.42 mm
Pins / Total PadsTopology
7P / 7Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
DFN-6(1.2x1.2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH443L (DFN-6(1.2x1.2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH443L (DFN-6(1.2x1.2))?

Manufactured by WCH, the CH443L is housed in a DFN-6(1.2x1.2) package with 7 pins and a 0.40 mm lead pitch. Key pins include: 1 (IN: Multiplexed I/O & Peripheral Pin IN (General)), 2 (S1A S1B 、 、 S1C S1D 、: Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General)), 3 (S2A S2B 、 、 S2C S2D 、: Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General)), 4 (DA DB 、 、 DC DD 、: Multiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General)), 5 (S1A S1B 、 、 S1C S1D 、: Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General)), 6 (S2A S2B 、 、 S2C S2D 、: Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH443L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH443L (DFN-6(1.2x1.2)) has a nominal body envelope of 1.20 × 1.20 mm, pitch e = 0.40 mm, and 7 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH443L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH443L (WCH, DFN-6(1.2x1.2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (7 pins) & CH445 / CH448 / CH440 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1INDigital_IOSignal terminal IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN. Supported peripheral buses: General.
2S1A S1B 、 、 S1C S1D 、Digital_IOSignal terminal S1A S1B 、 、 S1C S1D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S1A S1B 、 、 S1C S1D 、. Supported peripheral buses: General.
3S2A S2B 、 、 S2C S2D 、Digital_IOSignal terminal S2A S2B 、 、 S2C S2D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S2A S2B 、 、 S2C S2D 、. Supported peripheral buses: General.
4DA DB 、 、 DC DD 、Digital_IOSignal terminal DA DB 、 、 DC DD 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DA DB 、 、 DC DD 、. Supported peripheral buses: General.
5S1A S1B 、 、 S1C S1D 、Digital_IOSignal terminal S1A S1B 、 、 S1C S1D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S1A S1B 、 、 S1C S1D 、. Supported peripheral buses: General.
6S2A S2B 、 、 S2C S2D 、Digital_IOSignal terminal S2A S2B 、 、 S2C S2D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S2A S2B 、 、 S2C S2D 、. Supported peripheral buses: General.
7DA DB 、 、 DC DD 、Digital_IOSignal terminal DA DB 、 、 DC DD 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DA DB 、 、 DC DD 、. Supported peripheral buses: General.
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