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CH449F (QFN-24(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH449F

WCHID: C54973457QFN-24(4x4) · 25 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH449F (QFN-24(4x4))1PU_SDA2VDD3A0X A0Y 、4A0X A0Y 、5A1X A1Y 、6A1X A1Y 、7A2X A2Y 、8A2X A2Y 、9A3X A3Y 、10A3X A3Y 、11ADDR12RSTI#13GND25GND24SCL23SDA22B0X B0Y 、21B0X B0Y 、20B1X B1Y 、19B1X B1Y 、18B2X B2Y 、17B2X B2Y 、16B3X B3Y 、15B3X B3Y 、14LVR#Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PU_SDAI/OMultiplexed I/O & Peripheral Pin PU_SDA (I2C)
2VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
3A0X A0Y 、I/OMultiplexed I/O & Peripheral Pin A0X A0Y 、 (General)
4A0X A0Y 、I/OMultiplexed I/O & Peripheral Pin A0X A0Y 、 (General)
5A1X A1Y 、I/OMultiplexed I/O & Peripheral Pin A1X A1Y 、 (General)
6A1X A1Y 、I/OMultiplexed I/O & Peripheral Pin A1X A1Y 、 (General)
7A2X A2Y 、I/OMultiplexed I/O & Peripheral Pin A2X A2Y 、 (General)
8A2X A2Y 、I/OMultiplexed I/O & Peripheral Pin A2X A2Y 、 (General)
9A3X A3Y 、I/OMultiplexed I/O & Peripheral Pin A3X A3Y 、 (General)
10A3X A3Y 、I/OMultiplexed I/O & Peripheral Pin A3X A3Y 、 (General)
11ADDRI/OMultiplexed I/O & Peripheral Pin ADDR (General)
12RSTI#I/OMultiplexed I/O & Peripheral Pin RSTI# (General)
13GNDGNDGround Reference Pin (GND)
14LVR#I/OMultiplexed I/O & Peripheral Pin LVR# (General)
15B3X B3Y 、I/OMultiplexed I/O & Peripheral Pin B3X B3Y 、 (General)
16B3X B3Y 、I/OMultiplexed I/O & Peripheral Pin B3X B3Y 、 (General)
17B2X B2Y 、I/OMultiplexed I/O & Peripheral Pin B2X B2Y 、 (General)
18B2X B2Y 、I/OMultiplexed I/O & Peripheral Pin B2X B2Y 、 (General)
19B1X B1Y 、I/OMultiplexed I/O & Peripheral Pin B1X B1Y 、 (General)
20B1X B1Y 、I/OMultiplexed I/O & Peripheral Pin B1X B1Y 、 (General)
21B0X B0Y 、I/OMultiplexed I/O & Peripheral Pin B0X B0Y 、 (General)
22B0X B0Y 、I/OMultiplexed I/O & Peripheral Pin B0X B0Y 、 (General)
23SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
24SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
25GNDGNDGround Reference Pin (GND)
PIN 1 PU_SDA
I/O
Multiplexed I/O & Peripheral Pin PU_SDA (I2C)
Design note: 2线串行接口的SDA上拉电阻使能 ： 低电平 关闭内置电阻 高电平 使能内部上拉电阻 - ； -
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH449F (WCH · QFN-24(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH449F (QFN-24(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH449F (QFN-24(4x4)) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH449F (QFN-24(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH449F (QFN-24(4x4)) - 4. Package Dimensions (D×E×A)
QFN-24(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH449F (QFN-24(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH449F (QFN-24(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH449
P2 · p02_fig01EXACT PACKAGE
CH449F (QFN-24(4x4)) — 引脚号 引脚名称 类型 引脚说明 2 VDD 电源 正电源 13、0 GND 电源 公共接地，数字信号参考地 24 SCL 输入 2 线串行接口的时钟输入
引脚号 引脚名称 类型 引脚说明 2 VDD 电源 正电源 13、0 GND 电源 公共接地，数字信号参考地 24 SCL 输入 2 线串行接口的时钟输入
P7 · p07_fig01EXACT PACKAGE
CH449F (QFN-24(4x4)) — 说明：尺寸标注的单位是mm（毫米），引脚中心间距是标称值，除此之外的尺寸误差不大于±0.2mm。 QFN24-4*4
说明：尺寸标注的单位是mm（毫米），引脚中心间距是标称值，除此之外的尺寸误差不大于±0.2mm。 QFN24-4*4
P1 · p01_fig011575×923px
CH449F (QFN-24(4x4)) — 2、特点
2、特点
P2 · p02_fig01P2
CH449F (QFN-24(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P5 · p05_fig011725×2222px
CH449F (QFN-24(4x4)) — 6.4. 接口时序参数（测试条件：TA=25℃，VDD=5V 或VDD=3.3V，参考附图）
6.4. 接口时序参数（测试条件：TA=25℃，VDD=5V 或VDD=3.3V，参考附图）
P6 · p06_fig011723×452px
CH449F (QFN-24(4x4)) — CH449 手册 ６ | TSDA SDA 输入数据对SCL 上升沿的建立时间 30 nS THDA SDA 输入数据对SCL 上升沿的保持时间 20 nS TAA SDA 输出数据有效对SCL 下降沿的延时 5 40 nS TDH SDA 输出数据无效对SCL 下降沿的延时 5 60 nS Rate 平均数据传输速率 0 2M bps
CH449 手册 ６ | TSDA SDA 输入数据对SCL 上升沿的建立时间 30 nS THDA SDA 输入数据对SCL 上升沿的保持时间 20 nS TAA SDA 输出数据有效对SCL 下降沿的延时 5 40 nS TDH SDA 输出数据无效对SCL 下降沿的延时 5 60 nS Rate 平均数据传输速率 0 2M bps
P6 · p06_fig021491×451px
CH449F (QFN-24(4x4)) — 6.5. 其它时序参数（测试条件：TA=25℃，VDD=5V，VANA=0V，F=1MHz）
6.5. 其它时序参数（测试条件：TA=25℃，VDD=5V，VANA=0V，F=1MHz）
P6 · p06_fig031440×719px
CH449F (QFN-24(4x4)) — VCOM(V)
VCOM(V)
P6 · p06_fig02P6
CH449F (QFN-24(4x4)) — Datasheet Page 6 (p06_fig02)
Datasheet Page 6 (p06_fig02)

Technical Specifications & Part Details (CH449F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH449F (QFN-24(4x4)) is a 24-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-24(4x4))
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-24(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-24(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH449F (QFN-24(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH449F (QFN-24(4x4))?

Manufactured by WCH, the CH449F is housed in a QFN-24(4x4) package with 25 pins and a 0.50 mm lead pitch. Key pins include: 1 (PU_SDA: Multiplexed I/O & Peripheral Pin PU_SDA (I2C)), 2 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 3 (A0X A0Y 、: Multiplexed I/O & Peripheral Pin A0X A0Y 、 (General)), 4 (A0X A0Y 、: Multiplexed I/O & Peripheral Pin A0X A0Y 、 (General)), 5 (A1X A1Y 、: Multiplexed I/O & Peripheral Pin A1X A1Y 、 (General)), 6 (A1X A1Y 、: Multiplexed I/O & Peripheral Pin A1X A1Y 、 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH449F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH449F (QFN-24(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH449F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH449F (WCH, QFN-24(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & CH449 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PU_SDADigital_IOSignal terminal PU_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PU_SDA. Supported peripheral buses: I2C.
2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3A0X A0Y 、Digital_IOSignal terminal A0X A0Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0X A0Y 、. Supported peripheral buses: General.
4A0X A0Y 、Digital_IOSignal terminal A0X A0Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0X A0Y 、. Supported peripheral buses: General.
5A1X A1Y 、Digital_IOSignal terminal A1X A1Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1X A1Y 、. Supported peripheral buses: General.
6A1X A1Y 、Digital_IOSignal terminal A1X A1Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1X A1Y 、. Supported peripheral buses: General.
7A2X A2Y 、Digital_IOSignal terminal A2X A2Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2X A2Y 、. Supported peripheral buses: General.
8A2X A2Y 、Digital_IOSignal terminal A2X A2Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2X A2Y 、. Supported peripheral buses: General.
9A3X A3Y 、Digital_IOSignal terminal A3X A3Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3X A3Y 、. Supported peripheral buses: General.
10A3X A3Y 、Digital_IOSignal terminal A3X A3Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3X A3Y 、. Supported peripheral buses: General.
11ADDRDigital_IOSignal terminal ADDR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADDR. Supported peripheral buses: General.
12RSTI#Digital_IOSignal terminal RSTI# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTI#. Supported peripheral buses: General.
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14LVR#Digital_IOSignal terminal LVR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LVR#. Supported peripheral buses: General.
15B3X B3Y 、Digital_IOSignal terminal B3X B3Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B3X B3Y 、. Supported peripheral buses: General.
16B3X B3Y 、Digital_IOSignal terminal B3X B3Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B3X B3Y 、. Supported peripheral buses: General.
17B2X B2Y 、Digital_IOSignal terminal B2X B2Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B2X B2Y 、. Supported peripheral buses: General.
18B2X B2Y 、Digital_IOSignal terminal B2X B2Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B2X B2Y 、. Supported peripheral buses: General.
19B1X B1Y 、Digital_IOSignal terminal B1X B1Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B1X B1Y 、. Supported peripheral buses: General.
20B1X B1Y 、Digital_IOSignal terminal B1X B1Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B1X B1Y 、. Supported peripheral buses: General.
21B0X B0Y 、Digital_IOSignal terminal B0X B0Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B0X B0Y 、. Supported peripheral buses: General.
22B0X B0Y 、Digital_IOSignal terminal B0X B0Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B0X B0Y 、. Supported peripheral buses: General.
23SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
24SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
25GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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