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CH9431T (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9431T

WCHID: C54973454TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9431T (TSSOP-20)1CANT2CANR3CLKOUT4TX0RTS#5TX1RTS#6NC7TX2RTS#8OSC_OUT9OSC_IN10VSS20VDD19RESET#18CS#17MISO16MOSI15NC14SCK13INT#12RX0IP#11RX1IP#Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1CANTI/OMultiplexed I/O & Peripheral Pin CANT (CAN)
2CANRI/OMultiplexed I/O & Peripheral Pin CANR (CAN)
3CLKOUTI/OMultiplexed I/O & Peripheral Pin CLKOUT (General)
4TX0RTS#I/OMultiplexed I/O & Peripheral Pin TX0RTS# (General)
5TX1RTS#I/OMultiplexed I/O & Peripheral Pin TX1RTS# (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7TX2RTS#I/OMultiplexed I/O & Peripheral Pin TX2RTS# (General)
8OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
9OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
10VSSGNDGround Reference Pin (VSS)
11RX1IP#I/OMultiplexed I/O & Peripheral Pin RX1IP# (General)
12RX0IP#I/OMultiplexed I/O & Peripheral Pin RX0IP# (General)
13INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
14SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16MOSII/OMultiplexed I/O & Peripheral Pin MOSI (SPI)
17MISOI/OMultiplexed I/O & Peripheral Pin MISO (SPI)
18CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
19RESET#ISystem Enable & Hardware Reset (RESET#)
20VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
PIN 1 CANT
I/O
Multiplexed I/O & Peripheral Pin CANT (CAN)
Design note: Signal terminal CANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CANT. Supported peripheral buses: CAN.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 3 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9431T (WCH · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9431T (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9431T (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9431T (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9431T (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9431T (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9431T (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (3 figures · Page 1/1)
Showing 1–3 of 3 uncropped original figures for CH9431
P34 · p34_fig01EXACT PACKAGE
CH9431T (TSSOP-20) — 13.1 TSSOP20
13.1 TSSOP20
P2 · p02_fig011749×2677px
CH9431T (TSSOP-20) — V1.4 2
V1.4 2
P8 · p08_fig011740×386px
CH9431T (TSSOP-20) — V1.4 8
V1.4 8

Technical Specifications & Part Details (CH9431T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9431T (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, CAN, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, CAN, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9431T (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9431T (TSSOP-20)?

Manufactured by WCH, the CH9431T is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (CANT: Multiplexed I/O & Peripheral Pin CANT (CAN)), 2 (CANR: Multiplexed I/O & Peripheral Pin CANR (CAN)), 3 (CLKOUT: Multiplexed I/O & Peripheral Pin CLKOUT (General)), 4 (TX0RTS#: Multiplexed I/O & Peripheral Pin TX0RTS# (General)), 5 (TX1RTS#: Multiplexed I/O & Peripheral Pin TX1RTS# (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9431T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9431T (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9431T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9431T (WCH, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH9431 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1CANTRF_50OhmSignal terminal CANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CANT. Supported peripheral buses: CAN.
2CANRDigital_IOSignal terminal CANR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CANR. Supported peripheral buses: CAN.
3CLKOUTDigital_IOSignal terminal CLKOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKOUT. Supported peripheral buses: General.
4TX0RTS#Digital_IOSignal terminal TX0RTS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX0RTS#. Supported peripheral buses: General.
5TX1RTS#Digital_IOSignal terminal TX1RTS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX1RTS#. Supported peripheral buses: General.
6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7TX2RTS#Digital_IOSignal terminal TX2RTS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX2RTS#. Supported peripheral buses: General.
8OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
9OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
11RX1IP#Digital_IOSignal terminal RX1IP# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RX1IP#. Supported peripheral buses: General.
12RX0IP#Digital_IOSignal terminal RX0IP# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RX0IP#. Supported peripheral buses: General.
13INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
14SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
15NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16MOSIDigital_IOSignal terminal MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MOSI. Supported peripheral buses: SPI.
17MISODigital_IOSignal terminal MISO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MISO. Supported peripheral buses: SPI.
18CS#Digital_IOSignal terminal CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
19RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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