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ESP32-C5HR8-V1.2 (QFN-48(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-C5HR8-V1.2

ESPRESSIFID: C54951940QFN-48(6x6) · 49 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-C5HR8-V1.2 (QFN-48(6x6))1VDDA62GND3VDDA74XTAL_N5XTAL_P6VDDA87CHIP_PU8VDDPST19XTAL_32K_P10XTAL_32K_N11MTMS12MTDI13MTCK14MTDO15GPIO616GPIO717GPIO818GPIO919GPIO1020U0TXD21U0RXD22GPIO1323GPIO1424VDDPST225SPICS149GND48ANT_5G47GND46VDDA545VDDA444VDDA343GND42ANT_2G41VDDA240VDDA139VDDPST338GPIO2837GPIO2736GPIO2635GPIO2534GPIO2433GPIO2332SPID31SPICLK30SPIHD29VDD_SPI28SPIWP27SPIQ26SPICS0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=6.00mm · Pitch e=0.40mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDA6PowerPower Supply Input (VDDA6 — 3.3V VDD3P3 (3.0V ~ 3.6V))
2GNDGNDGround Reference Pin (GND)
3VDDA7PowerPower Supply Input (VDDA7 — 3.3V VDD3P3 (3.0V ~ 3.6V))
4XTAL_NI/OMultiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
5XTAL_PI/OMultiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
6VDDA8PowerPower Supply Input (VDDA8 — 3.3V VDD3P3 (3.0V ~ 3.6V))
7CHIP_PUISystem Enable & Hardware Reset (CHIP_PU)
8VDDPST1PowerPower Supply Input (VDDPST1 — 3.3V VDD3P3 (3.0V ~ 3.6V))
9XTAL_32K_PI/OMultiplexed I/O & Peripheral Pin XTAL_32K_P (RTC/CLK)
10XTAL_32K_NI/OMultiplexed I/O & Peripheral Pin XTAL_32K_N (RTC/CLK)
11MTMSI/OMultiplexed I/O & Peripheral Pin MTMS (SWD/JTAG)
12MTDII/OMultiplexed I/O & Peripheral Pin MTDI (SWD/JTAG)
13MTCKI/OMultiplexed I/O & Peripheral Pin MTCK (SWD/JTAG)
14MTDOI/OMultiplexed I/O & Peripheral Pin MTDO (SWD/JTAG)
15GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (General)
16GPIO7I/OMultiplexed I/O & Peripheral Pin GPIO7 (General)
17GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (General)
18GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
19GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (General)
20U0TXDI/OMultiplexed I/O & Peripheral Pin U0TXD (UART)
21U0RXDI/OMultiplexed I/O & Peripheral Pin U0RXD (UART)
22GPIO13I/OMultiplexed I/O & Peripheral Pin GPIO13 (General)
23GPIO14I/OMultiplexed I/O & Peripheral Pin GPIO14 (General)
24VDDPST2PowerPower Supply Input (VDDPST2 — 3.3V VDD3P3 (3.0V ~ 3.6V))
25SPICS1I/OMultiplexed I/O & Peripheral Pin SPICS1 (SPI)
26SPICS0I/OMultiplexed I/O & Peripheral Pin SPICS0 (SPI)
27SPIQI/OMultiplexed I/O & Peripheral Pin SPIQ (SPI)
28SPIWPI/OMultiplexed I/O & Peripheral Pin SPIWP (SPI)
29VDD_SPIPowerRegulated Power Output (VDD_SPI — 3.3V VDD3P3 (3.0V ~ 3.6V))
30SPIHDI/OMultiplexed I/O & Peripheral Pin SPIHD (SPI)
31SPICLKI/OMultiplexed I/O & Peripheral Pin SPICLK (SPI)
32SPIDI/OMultiplexed I/O & Peripheral Pin SPID (SPI)
33GPIO23I/OMultiplexed I/O & Peripheral Pin GPIO23 (General)
34GPIO24I/OMultiplexed I/O & Peripheral Pin GPIO24 (General)
35GPIO25I/OMultiplexed I/O & Peripheral Pin GPIO25 (General)
36GPIO26I/OMultiplexed I/O & Peripheral Pin GPIO26 (General)
37GPIO27I/OMultiplexed I/O & Peripheral Pin GPIO27 (General)
38GPIO28I/OMultiplexed I/O & Peripheral Pin GPIO28 (General)
39VDDPST3PowerPower Supply Input (VDDPST3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
40VDDA1PowerPower Supply Input (VDDA1 — 3.3V VDD3P3 (3.0V ~ 3.6V))
41VDDA2PowerPower Supply Input (VDDA2 — 3.3V VDD3P3 (3.0V ~ 3.6V))
42ANT_2GI/OMultiplexed I/O & Peripheral Pin ANT_2G (General)
43GNDGNDGround Reference Pin (GND)
44VDDA3PowerPower Supply Input (VDDA3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
45VDDA4PowerPower Supply Input (VDDA4 — 3.3V VDD3P3 (3.0V ~ 3.6V))
46VDDA5PowerPower Supply Input (VDDA5 — 3.3V VDD3P3 (3.0V ~ 3.6V))
47GNDGNDGround Reference Pin (GND)
48ANT_5GI/OMultiplexed I/O & Peripheral Pin ANT_5G (General)
49GNDGNDExposed Thermal & Ground Pad (GND)
PIN 1 VDDA6
Power
Power Supply Input (VDDA6 — 3.3V VDD3P3 (3.0V ~ 3.6V))
Design note: Primary positive power supply input (VDDA6) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-C5HR8-V1.2 (ESPRESSIF · QFN-48(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-C5HR8-V1.2 (QFN-48(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-C5HR8-V1.2 (QFN-48(6x6)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-C5HR8-V1.2 (QFN-48(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-C5HR8-V1.2 (QFN-48(6x6)) - 4. Package Dimensions (D×E×A)
QFN-48(6x6) · 6.00×6.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-C5HR8-V1.2 (QFN-48(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-C5HR8-V1.2 (QFN-48(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for ESP32-C5HF4 / ESP32-C5HR8
P81 · p81_fig01EXACT PACKAGE
ESP32-C5HR8-V1.2 (QFN-48(6x6)) — 图7-1. QFN48 (6×6 mm) 封装
图7-1. QFN48 (6×6 mm) 封装
P1 · p01_fig01336×313px
ESP32-C5HR8-V1.2 (QFN-48(6x6)) — 5) ESPRESSIF
5) ESPRESSIF
P2 · p02_fig011739×1898px
ESP32-C5HR8-V1.2 (QFN-48(6x6)) — ESP32-C5 功能框图
ESP32-C5 功能框图
P16 · p16_fig011792×1733px
ESP32-C5HR8-V1.2 (QFN-48(6x6)) — 图2-1. ESP32-C5HR2 & ESP32-C5HR8 管脚布局（俯视图）
图2-1. ESP32-C5HR2 & ESP32-C5HR8 管脚布局（俯视图）
P16 · p16_fig01P16
ESP32-C5HR8-V1.2 (QFN-48(6x6)) — Datasheet Page 16 (p16_fig01)
Datasheet Page 16 (p16_fig01)
P81 · p81_fig01P81
ESP32-C5HR8-V1.2 (QFN-48(6x6)) — Datasheet Page 81 (p81_fig01)
Datasheet Page 81 (p81_fig01)

Technical Specifications & Part Details (ESP32-C5HR8-V1.2)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-C5HR8-V1.2 (QFN-48(6x6)) is a 48-pin wireless wi-fi / bluetooth le soc module featuring a 6.00 × 6.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48(6x6))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (MTDI, MTDO): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.85 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-C5HR8-V1.2 (QFN-48(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-C5HR8-V1.2 (QFN-48(6x6))?

Manufactured by ESPRESSIF, the ESP32-C5HR8-V1.2 is housed in a QFN-48(6x6) package with 49 pins and a 0.40 mm lead pitch. Key pins include: 1 (VDDA6: Power Supply Input (VDDA6 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 2 (GND: Ground Reference Pin (GND)), 3 (VDDA7: Power Supply Input (VDDA7 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 4 (XTAL_N: Multiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)), 5 (XTAL_P: Multiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)), 6 (VDDA8: Power Supply Input (VDDA8 — 3.3V VDD3P3 (3.0V ~ 3.6V))).

What are the IPC-7351B PCB Footprint dimensions for ESP32-C5HR8-V1.2?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-C5HR8-V1.2 (QFN-48(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.40 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-C5HR8-V1.2?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-C5HR8-V1.2 (ESPRESSIF, QFN-48(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & ESP32-C5HF4 / ESP32-C5HR8 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDA6Power_InPrimary positive power supply input (VDDA6) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3VDDA7Power_InPrimary positive power supply input (VDDA7) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
4XTAL_NDigital_IOSignal terminal XTAL_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
5XTAL_PDigital_IOSignal terminal XTAL_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
6VDDA8Power_InPrimary positive power supply input (VDDA8) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
7CHIP_PUDigital_IOChip enable and power-on reset control input (CHIP_PU): High enables the SoC; Low powers down the chip into reset.
8VDDPST1Power_InPrimary positive power supply input (VDDPST1) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
9XTAL_32K_PDigital_IOSignal terminal XTAL_32K_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_32K_P. Supported peripheral buses: RTC/CLK.
10XTAL_32K_NDigital_IOSignal terminal XTAL_32K_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_32K_N. Supported peripheral buses: RTC/CLK.
11MTMSDigital_IOSignal terminal MTMS (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTMS. Supported peripheral buses: SWD/JTAG.
12MTDIDigital_IOSignal terminal MTDI (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDI. Supported peripheral buses: SWD/JTAG.
13MTCKDigital_IOSignal terminal MTCK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTCK. Supported peripheral buses: SWD/JTAG.
14MTDODigital_IOSignal terminal MTDO (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDO. Supported peripheral buses: SWD/JTAG.
15GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General.
16GPIO7Digital_IOSignal terminal GPIO7 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General.
17GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
18GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
19GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
20U0TXDDigital_IOSignal terminal U0TXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0TXD. Supported peripheral buses: UART.
21U0RXDDigital_IOSignal terminal U0RXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RXD. Supported peripheral buses: UART.
22GPIO13Digital_IOSignal terminal GPIO13 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO13. Supported peripheral buses: General.
23GPIO14Digital_IOSignal terminal GPIO14 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO14. Supported peripheral buses: General.
24VDDPST2Power_InPrimary positive power supply input (VDDPST2) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
25SPICS1Digital_IOSignal terminal SPICS1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICS1. Supported peripheral buses: SPI.
26SPICS0Digital_IOSignal terminal SPICS0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICS0. Supported peripheral buses: SPI.
27SPIQDigital_IOSignal terminal SPIQ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIQ. Supported peripheral buses: SPI.
28SPIWPDigital_IOSignal terminal SPIWP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIWP. Supported peripheral buses: SPI.
29VDD_SPIPower_OutRegulated power output rail (VDD_SPI) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
30SPIHDDigital_IOSignal terminal SPIHD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIHD. Supported peripheral buses: SPI.
31SPICLKDigital_IOSignal terminal SPICLK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICLK. Supported peripheral buses: SPI.
32SPIDDigital_IOSignal terminal SPID (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPID. Supported peripheral buses: SPI.
33GPIO23Digital_IOSignal terminal GPIO23 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO23. Supported peripheral buses: General.
34GPIO24Digital_IOSignal terminal GPIO24 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO24. Supported peripheral buses: General.
35GPIO25Digital_IOSignal terminal GPIO25 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO25. Supported peripheral buses: General.
36GPIO26Digital_IOSignal terminal GPIO26 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO26. Supported peripheral buses: General.
37GPIO27Digital_IOSignal terminal GPIO27 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO27. Supported peripheral buses: General.
38GPIO28Digital_IOSignal terminal GPIO28 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO28. Supported peripheral buses: General.
39VDDPST3Power_InPrimary positive power supply input (VDDPST3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
40VDDA1Power_InPrimary positive power supply input (VDDA1) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
41VDDA2Power_InPrimary positive power supply input (VDDA2) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
42ANT_2GRF_50OhmSignal terminal ANT_2G (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ANT_2G. Supported peripheral buses: General.
43GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
44VDDA3Power_InPrimary positive power supply input (VDDA3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
45VDDA4Power_InPrimary positive power supply input (VDDA4) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
46VDDA5Power_InPrimary positive power supply input (VDDA5) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48ANT_5GRF_50OhmSignal terminal ANT_5G (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ANT_5G. Supported peripheral buses: General.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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