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ESP32-P4NRW32X (QFN-104(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-P4NRW32X

ESPRESSIFID: C54540373QFN-104(10x10) · 105 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-P4NRW32X (QFN-104(10x10))1GPIO12GPIO23GPIO34GPIO45GPIO56GPIO67GPIO78GPIO89VDD_LP10GPIO911GPIO1012GPIO1113GPIO1214GPIO1315GPIO1416GPIO1517GPIO1618GPIO1719GPIO1820GPIO1921VDD_IO_022GPIO2023GPIO2124GPIO2225GPIO2326VDD_HP_027FLASH_CS28FLASH_Q29FLASH_WP30VDD_FLASHIO31FLASH_HOLD32FLASH_CK33FLASH_D34P3435P3536P3637P3738P3839P3940P4041P4142P4243P4344P4445P4546P4647P4748P4849P4950P5051P5152P5253P53105EPAD/GND104P104103P103102P102101P101100P10099P9998P9897P9796P9695P9594P9493P9392P9291P9190P9089P8988P8887P8786P8685P8584P8483P8382P8281P8180P8079P7978P7877P7776P7675P7574P7473P7372P7271P7170P7069P6968P6867P6766P6665P6564P6463P6362P6261P6160P6059P5958P5857P5756P5655P5554P54Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.873.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105E=10.00mm · Pitch e=0.35mmD=10.00mm-8-6-4-20246886420-2-4-6-8mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (105/105)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GPIO1I/OMultiplexed I/O & Peripheral Pin GPIO1 (General)
2GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
3GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
4GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (General)
5GPIO5I/OMultiplexed I/O & Peripheral Pin GPIO5 (General)
6GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (General)
7GPIO7I/OMultiplexed I/O & Peripheral Pin GPIO7 (General)
8GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (General)
9VDD_LPPowerPower Supply Input (VDD_LP — 3.3V VDD3P3 (3.0V ~ 3.6V))
10GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
11GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (General)
12GPIO11I/OMultiplexed I/O & Peripheral Pin GPIO11 (General)
13GPIO12I/OMultiplexed I/O & Peripheral Pin GPIO12 (General)
14GPIO13I/OMultiplexed I/O & Peripheral Pin GPIO13 (General)
15GPIO14I/OMultiplexed I/O & Peripheral Pin GPIO14 (General)
16GPIO15I/OMultiplexed I/O & Peripheral Pin GPIO15 (General)
17GPIO16I/OMultiplexed I/O & Peripheral Pin GPIO16 (General)
18GPIO17I/OMultiplexed I/O & Peripheral Pin GPIO17 (General)
19GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
20GPIO19I/OMultiplexed I/O & Peripheral Pin GPIO19 (General)
21VDD_IO_0PowerPower Supply Input (VDD_IO_0 — 3.3V VDD3P3 (3.0V ~ 3.6V))
22GPIO20I/OMultiplexed I/O & Peripheral Pin GPIO20 (General)
23GPIO21I/OMultiplexed I/O & Peripheral Pin GPIO21 (General)
24GPIO22I/OMultiplexed I/O & Peripheral Pin GPIO22 (General)
25GPIO23I/OMultiplexed I/O & Peripheral Pin GPIO23 (General)
26VDD_HP_0PowerPower Supply Input (VDD_HP_0 — 3.3V VDD3P3 (3.0V ~ 3.6V))
27FLASH_CSI/OMultiplexed I/O & Peripheral Pin FLASH_CS (General)
28FLASH_QI/OMultiplexed I/O & Peripheral Pin FLASH_Q (General)
29FLASH_WPI/OMultiplexed I/O & Peripheral Pin FLASH_WP (General)
30VDD_FLASHIOPowerPower Supply Input (VDD_FLASHIO — 3.3V VDD3P3 (3.0V ~ 3.6V))
31FLASH_HOLDI/OMultiplexed I/O & Peripheral Pin FLASH_HOLD (General)
32FLASH_CKI/OMultiplexed I/O & Peripheral Pin FLASH_CK (General)
33FLASH_DI/OMultiplexed I/O & Peripheral Pin FLASH_D (General)
34P34I/OSynthesized pin mapping for EDA symbol-footprint netlist
35P35I/OSynthesized pin mapping for EDA symbol-footprint netlist
36P36I/OSynthesized pin mapping for EDA symbol-footprint netlist
37P37I/OSynthesized pin mapping for EDA symbol-footprint netlist
38P38I/OSynthesized pin mapping for EDA symbol-footprint netlist
39P39I/OSynthesized pin mapping for EDA symbol-footprint netlist
40P40I/OSynthesized pin mapping for EDA symbol-footprint netlist
41P41I/OSynthesized pin mapping for EDA symbol-footprint netlist
42P42I/OSynthesized pin mapping for EDA symbol-footprint netlist
43P43I/OSynthesized pin mapping for EDA symbol-footprint netlist
44P44I/OSynthesized pin mapping for EDA symbol-footprint netlist
45P45I/OSynthesized pin mapping for EDA symbol-footprint netlist
46P46I/OSynthesized pin mapping for EDA symbol-footprint netlist
47P47I/OSynthesized pin mapping for EDA symbol-footprint netlist
48P48I/OSynthesized pin mapping for EDA symbol-footprint netlist
49P49I/OSynthesized pin mapping for EDA symbol-footprint netlist
50P50I/OSynthesized pin mapping for EDA symbol-footprint netlist
51P51I/OSynthesized pin mapping for EDA symbol-footprint netlist
52P52I/OSynthesized pin mapping for EDA symbol-footprint netlist
53P53I/OSynthesized pin mapping for EDA symbol-footprint netlist
54P54I/OSynthesized pin mapping for EDA symbol-footprint netlist
55P55I/OSynthesized pin mapping for EDA symbol-footprint netlist
56P56I/OSynthesized pin mapping for EDA symbol-footprint netlist
57P57I/OSynthesized pin mapping for EDA symbol-footprint netlist
58P58I/OSynthesized pin mapping for EDA symbol-footprint netlist
59P59I/OSynthesized pin mapping for EDA symbol-footprint netlist
60P60I/OSynthesized pin mapping for EDA symbol-footprint netlist
61P61I/OSynthesized pin mapping for EDA symbol-footprint netlist
62P62I/OSynthesized pin mapping for EDA symbol-footprint netlist
63P63I/OSynthesized pin mapping for EDA symbol-footprint netlist
64P64I/OSynthesized pin mapping for EDA symbol-footprint netlist
65P65I/OSynthesized pin mapping for EDA symbol-footprint netlist
66P66I/OSynthesized pin mapping for EDA symbol-footprint netlist
67P67I/OSynthesized pin mapping for EDA symbol-footprint netlist
68P68I/OSynthesized pin mapping for EDA symbol-footprint netlist
69P69I/OSynthesized pin mapping for EDA symbol-footprint netlist
70P70I/OSynthesized pin mapping for EDA symbol-footprint netlist
71P71I/OSynthesized pin mapping for EDA symbol-footprint netlist
72P72I/OSynthesized pin mapping for EDA symbol-footprint netlist
73P73I/OSynthesized pin mapping for EDA symbol-footprint netlist
74P74I/OSynthesized pin mapping for EDA symbol-footprint netlist
75P75I/OSynthesized pin mapping for EDA symbol-footprint netlist
76P76I/OSynthesized pin mapping for EDA symbol-footprint netlist
77P77I/OSynthesized pin mapping for EDA symbol-footprint netlist
78P78I/OSynthesized pin mapping for EDA symbol-footprint netlist
79P79I/OSynthesized pin mapping for EDA symbol-footprint netlist
80P80I/OSynthesized pin mapping for EDA symbol-footprint netlist
81P81I/OSynthesized pin mapping for EDA symbol-footprint netlist
82P82I/OSynthesized pin mapping for EDA symbol-footprint netlist
83P83I/OSynthesized pin mapping for EDA symbol-footprint netlist
84P84I/OSynthesized pin mapping for EDA symbol-footprint netlist
85P85I/OSynthesized pin mapping for EDA symbol-footprint netlist
86P86I/OSynthesized pin mapping for EDA symbol-footprint netlist
87P87I/OSynthesized pin mapping for EDA symbol-footprint netlist
88P88I/OSynthesized pin mapping for EDA symbol-footprint netlist
89P89I/OSynthesized pin mapping for EDA symbol-footprint netlist
90P90I/OSynthesized pin mapping for EDA symbol-footprint netlist
91P91I/OSynthesized pin mapping for EDA symbol-footprint netlist
92P92I/OSynthesized pin mapping for EDA symbol-footprint netlist
93P93I/OSynthesized pin mapping for EDA symbol-footprint netlist
94P94I/OSynthesized pin mapping for EDA symbol-footprint netlist
95P95I/OSynthesized pin mapping for EDA symbol-footprint netlist
96P96I/OSynthesized pin mapping for EDA symbol-footprint netlist
97P97I/OSynthesized pin mapping for EDA symbol-footprint netlist
98P98I/OSynthesized pin mapping for EDA symbol-footprint netlist
99P99I/OSynthesized pin mapping for EDA symbol-footprint netlist
100P100I/OSynthesized pin mapping for EDA symbol-footprint netlist
101P101I/OSynthesized pin mapping for EDA symbol-footprint netlist
102P102I/OSynthesized pin mapping for EDA symbol-footprint netlist
103P103I/OSynthesized pin mapping for EDA symbol-footprint netlist
104P104I/OSynthesized pin mapping for EDA symbol-footprint netlist
105EPAD/GNDI/OSynthesized pin mapping for EDA symbol-footprint netlist
PIN 1 GPIO1
I/O
Multiplexed I/O & Peripheral Pin GPIO1 (General)
Design note: Signal terminal GPIO1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-P4NRW32X (ESPRESSIF · QFN-104(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-P4NRW32X (QFN-104(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-P4NRW32X (QFN-104(10x10)) - 2. Standard Pinout (Top View)
True package pinout (105 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-P4NRW32X (QFN-104(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-P4NRW32X (QFN-104(10x10)) - 4. Package Dimensions (D×E×A)
QFN-104(10x10) · 10.00×10.00mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-P4NRW32X (QFN-104(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (105 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-P4NRW32X (QFN-104(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (ESP32-P4NRW32X)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-P4NRW32X (QFN-104(10x10)) is a 32-pin wireless wi-fi / bluetooth le soc module featuring a 10.00 × 10.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-104(10x10))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol105 auto-grouped pins
OK
IPC-7351B Land Pattern105 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteEPAD 7.50×7.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-104(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.35mm
Pad Size (W × L)Level B
0.20 × 0.75 mm
Pins / Total PadsTopology
105P / 105Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-P4NRW32X (QFN-104(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-P4NRW32X (QFN-104(10x10))?

Manufactured by ESPRESSIF, the ESP32-P4NRW32X is housed in a QFN-104(10x10) package with 105 pins and a 0.35 mm lead pitch. Key pins include: 1 (GPIO1: Multiplexed I/O & Peripheral Pin GPIO1 (General)), 2 (GPIO2: Multiplexed I/O & Peripheral Pin GPIO2 (General)), 3 (GPIO3: Multiplexed I/O & Peripheral Pin GPIO3 (General)), 4 (GPIO4: Multiplexed I/O & Peripheral Pin GPIO4 (General)), 5 (GPIO5: Multiplexed I/O & Peripheral Pin GPIO5 (General)), 6 (GPIO6: Multiplexed I/O & Peripheral Pin GPIO6 (General)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-P4NRW32X?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-P4NRW32X (QFN-104(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.35 mm, and 105 copper pads plus a central exposed thermal pad (EPAD) of 7.50 × 7.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-P4NRW32X?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-P4NRW32X (ESPRESSIF, QFN-104(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (105 pins) & ESP32-P4NRW32X Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GPIO1Digital_IOSignal terminal GPIO1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
2GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
3GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
4GPIO4Digital_IOSignal terminal GPIO4 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General.
5GPIO5Digital_IOSignal terminal GPIO5 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO5. Supported peripheral buses: General.
6GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General.
7GPIO7Digital_IOSignal terminal GPIO7 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General.
8GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
9VDD_LPPower_InPrimary positive power supply input (VDD_LP) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
10GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
11GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
12GPIO11Digital_IOSignal terminal GPIO11 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO11. Supported peripheral buses: General.
13GPIO12Digital_IOSignal terminal GPIO12 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO12. Supported peripheral buses: General.
14GPIO13Digital_IOSignal terminal GPIO13 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO13. Supported peripheral buses: General.
15GPIO14Digital_IOSignal terminal GPIO14 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO14. Supported peripheral buses: General.
16GPIO15Digital_IOSignal terminal GPIO15 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO15. Supported peripheral buses: General.
17GPIO16Digital_IOSignal terminal GPIO16 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO16. Supported peripheral buses: General.
18GPIO17Digital_IOSignal terminal GPIO17 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO17. Supported peripheral buses: General.
19GPIO18Digital_IOSignal terminal GPIO18 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
20GPIO19Digital_IOSignal terminal GPIO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: General.
21VDD_IO_0Power_InPrimary positive power supply input (VDD_IO_0) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
22GPIO20Digital_IOSignal terminal GPIO20 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO20. Supported peripheral buses: General.
23GPIO21Digital_IOSignal terminal GPIO21 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO21. Supported peripheral buses: General.
24GPIO22Digital_IOSignal terminal GPIO22 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO22. Supported peripheral buses: General.
25GPIO23Digital_IOSignal terminal GPIO23 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO23. Supported peripheral buses: General.
26VDD_HP_0Power_InPrimary positive power supply input (VDD_HP_0) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
27FLASH_CSDigital_IOSignal terminal FLASH_CS (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: FLASH_CS. Supported peripheral buses: General.
28FLASH_QDigital_IOSignal terminal FLASH_Q (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: FLASH_Q. Supported peripheral buses: General.
29FLASH_WPDigital_IOSignal terminal FLASH_WP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: FLASH_WP. Supported peripheral buses: General.
30VDD_FLASHIOPower_InPrimary positive power supply input (VDD_FLASHIO) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
31FLASH_HOLDDigital_IOSignal terminal FLASH_HOLD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: FLASH_HOLD. Supported peripheral buses: General.
32FLASH_CKDigital_IOSignal terminal FLASH_CK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: FLASH_CK. Supported peripheral buses: General.
33FLASH_DDigital_IOSignal terminal FLASH_D (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: FLASH_D. Supported peripheral buses: General.
34P34Digital_IOP34 (ESP32-P4NRW32X)
35P35Digital_IOP35 (ESP32-P4NRW32X)
36P36Digital_IOP36 (ESP32-P4NRW32X)
37P37Digital_IOP37 (ESP32-P4NRW32X)
38P38Digital_IOP38 (ESP32-P4NRW32X)
39P39Digital_IOP39 (ESP32-P4NRW32X)
40P40Digital_IOP40 (ESP32-P4NRW32X)
41P41Digital_IOP41 (ESP32-P4NRW32X)
42P42Digital_IOP42 (ESP32-P4NRW32X)
43P43Digital_IOP43 (ESP32-P4NRW32X)
44P44Digital_IOP44 (ESP32-P4NRW32X)
45P45Digital_IOP45 (ESP32-P4NRW32X)
46P46Digital_IOP46 (ESP32-P4NRW32X)
47P47Digital_IOP47 (ESP32-P4NRW32X)
48P48Digital_IOP48 (ESP32-P4NRW32X)
49P49Digital_IOP49 (ESP32-P4NRW32X)
50P50Digital_IOP50 (ESP32-P4NRW32X)
51P51Digital_IOP51 (ESP32-P4NRW32X)
52P52Digital_IOP52 (ESP32-P4NRW32X)
53P53Digital_IOP53 (ESP32-P4NRW32X)
54P54Digital_IOP54 (ESP32-P4NRW32X)
55P55Digital_IOP55 (ESP32-P4NRW32X)
56P56Digital_IOP56 (ESP32-P4NRW32X)
57P57Digital_IOP57 (ESP32-P4NRW32X)
58P58Digital_IOP58 (ESP32-P4NRW32X)
59P59Digital_IOP59 (ESP32-P4NRW32X)
60P60Digital_IOP60 (ESP32-P4NRW32X)
61P61Digital_IOP61 (ESP32-P4NRW32X)
62P62Digital_IOP62 (ESP32-P4NRW32X)
63P63Digital_IOP63 (ESP32-P4NRW32X)
64P64Digital_IOP64 (ESP32-P4NRW32X)
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