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CH9432D (QFN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9432D

WCHID: C54426071QFN-20(3x3) · 21 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9432D (QFN-20(3x3))1PIN12 PIN13 2PIN7 PIN8 、3PIN2 PIN3 、4PIN145PIN166SEL/GPIO47TXD18RXD19TNOW0/GPIO510TNOW1/GPIO611SCS#/WAKE21GND20SDO/IIC_AD19SDI/SDA18SCK/SCL17RTS1/GPIO316CTS1/GPIO215RTS0/GPIO114CTS0/GPIO013RXD012TXD0Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.40mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PIN12 PIN13 、I/OMultiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)
2PIN7 PIN8 、I/OMultiplexed I/O & Peripheral Pin PIN7 PIN8 、 (UART)
3PIN2 PIN3 、I/OMultiplexed I/O & Peripheral Pin PIN2 PIN3 、 (RTC/CLK)
4PIN14I/OMultiplexed I/O & Peripheral Pin PIN14 (UART)
5PIN16I/OMultiplexed I/O & Peripheral Pin PIN16 (UART)
6SEL/GPIO4I/OMultiplexed I/O & Peripheral Pin SEL/GPIO4 (General)
7TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
8RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
9TNOW0/GPIO5I/OMultiplexed I/O & Peripheral Pin TNOW0/GPIO5 (General)
10TNOW1/GPIO6I/OMultiplexed I/O & Peripheral Pin TNOW1/GPIO6 (General)
11SCS#/WAKEI/OMultiplexed I/O & Peripheral Pin SCS#/WAKE (General)
12TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
13RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
14CTS0/GPIO0I/OMultiplexed I/O & Peripheral Pin CTS0/GPIO0 (UART)
15RTS0/GPIO1I/OMultiplexed I/O & Peripheral Pin RTS0/GPIO1 (UART)
16CTS1/GPIO2I/OMultiplexed I/O & Peripheral Pin CTS1/GPIO2 (UART)
17RTS1/GPIO3I/OMultiplexed I/O & Peripheral Pin RTS1/GPIO3 (UART)
18SCK/SCLI/OMultiplexed I/O & Peripheral Pin SCK/SCL (SPI, I2C)
19SDI/SDAI/OMultiplexed I/O & Peripheral Pin SDI/SDA (I2C)
20SDO/IIC_ADI/OMultiplexed I/O & Peripheral Pin SDO/IIC_AD (General)
21GNDGNDGround Reference Pin (GND)
PIN 1 PIN12 PIN13 、
I/O
Multiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)
Design note: UART0_TXRX_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9432D (WCH · QFN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9432D (QFN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9432D (QFN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9432D (QFN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9432D (QFN-20(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9432D (QFN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9432D (QFN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH9432
P2 · p02_fig01EXACT PACKAGE
CH9432D (QFN-20(3x3)) — V1.0 2
V1.0 2
P1 · p01_fig011493×566px
CH9432D (QFN-20(3x3)) — 2、特点
2、特点
P1 · p01_fig01P1
CH9432D (QFN-20(3x3)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P17 · p17_fig011361×775px
CH9432D (QFN-20(3x3)) — CH9432 手册 https://wch.cn
CH9432 手册 https://wch.cn
P17 · p17_fig021754×1349px
CH9432D (QFN-20(3x3)) — SCS#
SCS#
P17 · p17_fig031754×881px
CH9432D (QFN-20(3x3)) — V1.0 17
V1.0 17
P18 · p18_fig011761×1127px
CH9432D (QFN-20(3x3)) — 5)、关闭DLAB
5)、关闭DLAB
P18 · p18_fig02956×559px
CH9432D (QFN-20(3x3)) — 5)、关闭DLAB
5)、关闭DLAB
P18 · p18_fig031002×582px
CH9432D (QFN-20(3x3)) — V1.0 18
V1.0 18
P19 · p19_fig011763×1193px
CH9432D (QFN-20(3x3)) — CH9432 手册 https://wch.cn
CH9432 手册 https://wch.cn
P19 · p19_fig021814×1187px
CH9432D (QFN-20(3x3)) — 11.4 写串口数据 例：CH9432 串口1 发送2 字节数据0xAA、0xBB 1）、设置FIFO 控制器
11.4 写串口数据 例：CH9432 串口1 发送2 字节数据0xAA、0xBB 1）、设置FIFO 控制器

Technical Specifications & Part Details (CH9432D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9432D (QFN-20(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, SPI, I2C, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, SPI, I2C, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.90×1.90mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9432D (QFN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9432D (QFN-20(3x3))?

Manufactured by WCH, the CH9432D is housed in a QFN-20(3x3) package with 21 pins and a 0.40 mm lead pitch. Key pins include: 1 (PIN12 PIN13 、: Multiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)), 2 (PIN7 PIN8 、: Multiplexed I/O & Peripheral Pin PIN7 PIN8 、 (UART)), 3 (PIN2 PIN3 、: Multiplexed I/O & Peripheral Pin PIN2 PIN3 、 (RTC/CLK)), 4 (PIN14: Multiplexed I/O & Peripheral Pin PIN14 (UART)), 5 (PIN16: Multiplexed I/O & Peripheral Pin PIN16 (UART)), 6 (SEL/GPIO4: Multiplexed I/O & Peripheral Pin SEL/GPIO4 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9432D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9432D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.90 × 1.90 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9432D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9432D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH9432 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PIN12 PIN13 、Digital_IOSignal terminal PIN12 PIN13 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN12 PIN13 、. Supported peripheral buses: UART.
2PIN7 PIN8 、Digital_IOSignal terminal PIN7 PIN8 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN7 PIN8 、. Supported peripheral buses: UART.
3PIN2 PIN3 、Digital_IOSignal terminal PIN2 PIN3 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN2 PIN3 、. Supported peripheral buses: RTC/CLK.
4PIN14Digital_IOSignal terminal PIN14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN14. Supported peripheral buses: UART.
5PIN16Digital_IOSignal terminal PIN16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN16. Supported peripheral buses: UART.
6SEL/GPIO4Digital_IOSignal terminal SEL/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL/GPIO4. Supported peripheral buses: General.
7TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
8RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
9TNOW0/GPIO5Digital_IOSignal terminal TNOW0/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW0/GPIO5. Supported peripheral buses: General.
10TNOW1/GPIO6Digital_IOSignal terminal TNOW1/GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW1/GPIO6. Supported peripheral buses: General.
11SCS#/WAKEDigital_IOSignal terminal SCS#/WAKE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS#/WAKE. Supported peripheral buses: General.
12TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
13RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
14CTS0/GPIO0Digital_IOSignal terminal CTS0/GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0/GPIO0. Supported peripheral buses: UART.
15RTS0/GPIO1Digital_IOSignal terminal RTS0/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0/GPIO1. Supported peripheral buses: UART.
16CTS1/GPIO2Digital_IOSignal terminal CTS1/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1/GPIO2. Supported peripheral buses: UART.
17RTS1/GPIO3Digital_IOSignal terminal RTS1/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1/GPIO3. Supported peripheral buses: UART.
18SCK/SCLDigital_IOSignal terminal SCK/SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK/SCL. Supported peripheral buses: SPI, I2C.
19SDI/SDADigital_IOSignal terminal SDI/SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI/SDA. Supported peripheral buses: I2C.
20SDO/IIC_ADDigital_IOSignal terminal SDO/IIC_AD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO/IIC_AD. Supported peripheral buses: General.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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