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ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-C6-WROOM-1-N8

ESPRESSIFID: C5366877SMD,25.5x18mm · 37 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm)1GPIO923V33EN4IO45IO56IO67IO78IO09IO110IO811IO1012IO1113IO1214IO1315IO916IO1817IO1918IO2019IO2137GND36GND35GND34GND33GND32GND31GND30GND29EPAD28GND27IO226IO325TXD024RXD023IO1522NC21IO2320IO22Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (6.7mm)12345678910111213141516171819202122232425262728293031323334353637E=18.00mm · Pitch e=1.27mmD=25.50mm-16-14-12-10-8-6-4-20246810121416191715131197531-1-3-5-7-9-11-13-15-17-19mm
3. 3D CAD MODEL
Package Body: 18.00mm × 25.50mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (37/37)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
23V3PowerPower Supply Input (3V3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
3ENISystem Enable & Hardware Reset (EN)
4IO4I/OMultiplexed I/O & Peripheral Pin IO4 (UART, SPI, ADC, SWD/JTAG)
5IO5I/OMultiplexed I/O & Peripheral Pin IO5 (UART, SPI, ADC, SWD/JTAG)
6IO6I/OMultiplexed I/O & Peripheral Pin IO6 (SPI, I2C, ADC, SWD/JTAG)
7IO7I/OMultiplexed I/O & Peripheral Pin IO7 (SPI, I2C, SWD/JTAG)
8IO0I/OMultiplexed I/O & Peripheral Pin IO0 (UART, ADC, RTC/CLK)
9IO1I/OMultiplexed I/O & Peripheral Pin IO1 (UART, ADC, RTC/CLK)
10IO8I/OMultiplexed I/O & Peripheral Pin IO8 (General)
11IO10I/OMultiplexed I/O & Peripheral Pin IO10 (General)
12IO11I/OMultiplexed I/O & Peripheral Pin IO11 (General)
13IO12I/OMultiplexed I/O & Peripheral Pin IO12 (USB)
14IO13I/OMultiplexed I/O & Peripheral Pin IO13 (USB)
15IO9I/OMultiplexed I/O & Peripheral Pin IO9 (General)
16IO18I/OMultiplexed I/O & Peripheral Pin IO18 (SPI)
17IO19I/OMultiplexed I/O & Peripheral Pin IO19 (SPI)
18IO20I/OMultiplexed I/O & Peripheral Pin IO20 (SPI)
19IO21I/OMultiplexed I/O & Peripheral Pin IO21 (SPI)
20IO22I/OMultiplexed I/O & Peripheral Pin IO22 (General)
21IO23I/OMultiplexed I/O & Peripheral Pin IO23 (General)
22NCI/OMultiplexed I/O & Peripheral Pin NC (General)
23IO15I/OMultiplexed I/O & Peripheral Pin IO15 (General)
24RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART, SPI)
25TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART, SPI)
26IO3I/OMultiplexed I/O & Peripheral Pin IO3 (UART, ADC)
27IO2I/OMultiplexed I/O & Peripheral Pin IO2 (UART, SPI, ADC)
28GNDGNDGround Reference Pin (GND)
29EPADGNDExposed Thermal & Ground Pad (EPAD)
30GNDGNDGround Reference Pin (GND)
31GNDGNDGround Reference Pin (GND)
32GNDGNDGround Reference Pin (GND)
33GNDGNDGround Reference Pin (GND)
34GNDGNDGround Reference Pin (GND)
35GNDGNDGround Reference Pin (GND)
36GNDGNDGround Reference Pin (GND)
37GNDGNDGround Reference Pin (GND)
PIN 1 GPIO9
I/O
Multiplexed I/O & Peripheral Pin GPIO9 (General)
Design note: Signal terminal GPIO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-C6-WROOM-1-N8 (ESPRESSIF · SMD,25.5x18mm)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) - 2. Standard Pinout (Top View)
True package pinout (37 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) - 4. Package Dimensions (D×E×A)
SMD,25.5x18mm · 18.00×25.50mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) - 5. Recommended Land Pattern
IPC-7351B Footprint (37 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for ESP32-C6-WROOM
P1 · p01_fig01EXACT PACKAGE
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — ESP32-C6-WROOM-1 ESP32-C6-WROOM-1U @ €SPRESSIF ESP32-C6-WROOM-1 sca” Sa es iOF ESP32-C6-WROOM-1
ESP32-C6-WROOM-1 ESP32-C6-WROOM-1U @ €SPRESSIF ESP32-C6-WROOM-1 sca” Sa es iOF ESP32-C6-WROOM-1
P1 · p01_fig02EXACT PACKAGE
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — ESP32-C6-WROOM-1 ESP32-C6-WROOM-1U @ €SPRESSIF ESP32-C6-WROOM-1U aoaman Fae OF ESP32-C6-WROOM-1U
ESP32-C6-WROOM-1 ESP32-C6-WROOM-1U @ €SPRESSIF ESP32-C6-WROOM-1U aoaman Fae OF ESP32-C6-WROOM-1U
P26 · p26_fig01EXACT PACKAGE
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — 图5: ESP32-C6-WROOM-1 原理图
图5: ESP32-C6-WROOM-1 原理图
P29 · p29_fig01EXACT PACKAGE
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — 图8: ESP32-C6-WROOM-1 模组尺寸
图8: ESP32-C6-WROOM-1 模组尺寸
P29 · p29_fig02EXACT PACKAGE
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — 图8: ESP32-C6-WROOM-1 模组尺寸
图8: ESP32-C6-WROOM-1 模组尺寸
P30 · p30_fig01EXACT PACKAGE
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — 图10: ESP32-C6-WROOM-1 推荐PCB 封装图形
图10: ESP32-C6-WROOM-1 推荐PCB 封装图形
P1 · p01_fig03646×314px
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — www.espressif.com
www.espressif.com
P1 · p01_fig02P1
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P12 · p12_fig01869×717px
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — 图4: Strapping 管脚的时序参数图
图4: Strapping 管脚的时序参数图
P26 · p26_fig021114×1308px
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — vary with the actual PCB board.
vary with the actual PCB board.
P28 · p28_fig011804×836px
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — 图7: 外围设计原理图
图7: 外围设计原理图
P28 · p28_fig01P28
ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) — Datasheet Page 28 (p28_fig01)
Datasheet Page 28 (p28_fig01)
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (ESP32-C6-WROOM-1-N8)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) is a 37-pin wireless wi-fi / bluetooth le soc module featuring a 25.50 × 18.00 × 3.10 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.0 ~ 3.6 V supply operation across 85 °C – 105 °C with integrated Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0 ~ 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
85 °C – 105 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
25.50 × 18.00 × 3.10 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD,25.5x18mm)
Pin Count & Lead PitchN / e
37 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (IO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol37 auto-grouped pins
OK
IPC-7351B Land Pattern37 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SMD,25.5x18mm)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
25.50 × 18.00 mm
Height (A) & Pitch (e)IPC-7351B
A=3.10mm · e=1.27mm
Pad Size (W × L)Level B
0.90 × 1.50 mm
Pins / Total PadsTopology
37P / 37Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm)?

Manufactured by ESPRESSIF, the ESP32-C6-WROOM-1-N8 is housed in a SMD,25.5x18mm package with 37 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.0 ~ 3.6 V. Key pins include: 1 (GPIO9: Multiplexed I/O & Peripheral Pin GPIO9 (General)), 2 (3V3: Power Supply Input (3V3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 3 (EN: System Enable & Hardware Reset (EN)), 4 (IO4: Multiplexed I/O & Peripheral Pin IO4 (UART, SPI, ADC, SWD/JTAG)), 5 (IO5: Multiplexed I/O & Peripheral Pin IO5 (UART, SPI, ADC, SWD/JTAG)), 6 (IO6: Multiplexed I/O & Peripheral Pin IO6 (SPI, I2C, ADC, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-C6-WROOM-1-N8?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-C6-WROOM-1-N8 (SMD,25.5x18mm) has a nominal body envelope of 18.00 × 25.50 mm, pitch e = 1.27 mm, and 37 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-C6-WROOM-1-N8?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-C6-WROOM-1-N8 (ESPRESSIF, SMD,25.5x18mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (37 pins) & ESP32-C6-WROOM Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
23V3Power_InPrimary positive power supply input (3V3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
3ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
4IO4Digital_IOSignal terminal IO4 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTMS, GPIO4, ADC1_CH4, FSPIHD. Supported peripheral buses: UART, SPI, ADC, SWD/JTAG.
5IO5Digital_IOSignal terminal IO5 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDI, GPIO5, ADC1_CH5, FSPIWP. Supported peripheral buses: UART, SPI, ADC, SWD/JTAG.
6IO6Digital_IOSignal terminal IO6 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTCK, GPIO6, I2C_SDA, ADC1_CH6, FSPICLK. Supported peripheral buses: SPI, I2C, ADC, SWD/JTAG.
7IO7Digital_IOSignal terminal IO7 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDO, GPIO7, I2C_SCL, FSPID. Supported peripheral buses: SPI, I2C, SWD/JTAG.
8IO0Digital_IOSignal terminal IO0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO0, ADC1_CH0. Supported peripheral buses: UART, ADC, RTC/CLK.
9IO1Digital_IOSignal terminal IO1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO1, ADC1_CH1. Supported peripheral buses: UART, ADC, RTC/CLK.
10IO8Digital_IOSignal terminal IO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
11IO10Digital_IOSignal terminal IO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
12IO11Digital_IOSignal terminal IO11 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO11. Supported peripheral buses: General.
13IO12Digital_IOSignal terminal IO12 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO12. Supported peripheral buses: USB.
14IO13Digital_IOSignal terminal IO13 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO13. Supported peripheral buses: USB.
15IO9Digital_IOSignal terminal IO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
16IO18Digital_IOSignal terminal IO18 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO18, FSPICS2. Supported peripheral buses: SPI.
17IO19Digital_IOSignal terminal IO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: SPI.
18IO20Digital_IOSignal terminal IO20 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO20, FSPICS4. Supported peripheral buses: SPI.
19IO21Digital_IOSignal terminal IO21 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO21, FSPICS5. Supported peripheral buses: SPI.
20IO22Digital_IOSignal terminal IO22 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO22. Supported peripheral buses: General.
21IO23Digital_IOSignal terminal IO23 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO23. Supported peripheral buses: General.
22NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
23IO15Digital_IOSignal terminal IO15 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO15. Supported peripheral buses: General.
24RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RXD, GPIO17, FSPICS1. Supported peripheral buses: UART, SPI.
25TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0TXD, GPIO16, FSPICS0. Supported peripheral buses: UART, SPI.
26IO3Digital_IOSignal terminal IO3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO3, ADC1_CH3. Supported peripheral buses: UART, ADC.
27IO2Digital_IOSignal terminal IO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO2, ADC1_CH2, FSPIQ. Supported peripheral buses: UART, SPI, ADC.
28GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
29EPADGNDBottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
30GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
31GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
32GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
34GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
35GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
36GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
37GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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