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CH9438F (QFN-32(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9438F

WCHID: C53511579QFN-32(4x4) · 33 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9438F (QFN-32(4x4))1PIN30 PIN29 2PIN10 PIN11 3PIN24 PIN19 4PIN16 PIN17 5PIN27 PIN28 6PIN23 PIN18 7/GPIO7 RST#8/TNOW09/TNOW1 /GPIO10TXD111RXD112SCS13SCK14SDO15SDI16TXD317RXD333GND32V CC31VIO30TXD029RXD028RXD427TXD426RXD725TXD724TXD223TXD522/TNOW621RXD620TXD619RXD218RXD5Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.227.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PIN30 PIN29 、I/OMultiplexed I/O & Peripheral Pin PIN30 PIN29 、 (UART)
2PIN10 PIN11 、I/OMultiplexed I/O & Peripheral Pin PIN10 PIN11 、 (UART)
3PIN24 PIN19 、I/OMultiplexed I/O & Peripheral Pin PIN24 PIN19 、 (UART)
4PIN16 PIN17 、I/OMultiplexed I/O & Peripheral Pin PIN16 PIN17 、 (UART)
5PIN27 PIN28 、I/OMultiplexed I/O & Peripheral Pin PIN27 PIN28 、 (UART)
6PIN23 PIN18 、I/OMultiplexed I/O & Peripheral Pin PIN23 PIN18 、 (UART)
7/GPIO7 RST#I/OMultiplexed I/O & Peripheral Pin /GPIO7 RST# (General)
8/TNOW0I/OMultiplexed I/O & Peripheral Pin /TNOW0 (General)
9/TNOW1 /GPIO1I/OMultiplexed I/O & Peripheral Pin /TNOW1 /GPIO1 (General)
10TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
11RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
12SCSI/OMultiplexed I/O & Peripheral Pin SCS (General)
13SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
14SDOI/OMultiplexed I/O & Peripheral Pin SDO (General)
15SDII/OMultiplexed I/O & Peripheral Pin SDI (General)
16TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
17RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
18RXD5I/OMultiplexed I/O & Peripheral Pin RXD5 (UART)
19RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
20TXD6I/OMultiplexed I/O & Peripheral Pin TXD6 (UART)
21RXD6I/OMultiplexed I/O & Peripheral Pin RXD6 (UART)
22/TNOW6I/OMultiplexed I/O & Peripheral Pin /TNOW6 (General)
23TXD5I/OMultiplexed I/O & Peripheral Pin TXD5 (UART)
24TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
25TXD7I/OMultiplexed I/O & Peripheral Pin TXD7 (UART)
26RXD7I/OMultiplexed I/O & Peripheral Pin RXD7 (UART)
27TXD4I/OMultiplexed I/O & Peripheral Pin TXD4 (UART)
28RXD4I/OMultiplexed I/O & Peripheral Pin RXD4 (UART)
29RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
30TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
31VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
32V CCI/OMultiplexed I/O & Peripheral Pin V CC (General)
33GNDGNDGround Reference Pin (GND)
PIN 1 PIN30 PIN29 、
I/O
Multiplexed I/O & Peripheral Pin PIN30 PIN29 、 (UART)
Design note: UART0_TXRX_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9438F (WCH · QFN-32(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9438F (QFN-32(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9438F (QFN-32(4x4)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9438F (QFN-32(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9438F (QFN-32(4x4)) - 4. Package Dimensions (D×E×A)
QFN-32(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9438F (QFN-32(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9438F (QFN-32(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH9438
P2 · p02_fig01EXACT PACKAGE
CH9438F (QFN-32(4x4)) — 4、引脚排列
4、引脚排列
P1 · p01_fig011519×814px
CH9438F (QFN-32(4x4)) — 2、特点
2、特点
P14 · p14_fig011431×871px
CH9438F (QFN-32(4x4)) — 11.2 初始化串口 例1：CH9438 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1）、读出串口1 的LCR 寄存器值，假设读出0x00。
11.2 初始化串口 例1：CH9438 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1）、读出串口1 的LCR 寄存器值，假设读出0x00。
P14 · p14_fig021195×648px
CH9438F (QFN-32(4x4)) — 2）、写串口1 的LCR 寄存器值，设DLAB 位，设8Bit 数据位，1Bit 停止位，无校验。
2）、写串口1 的LCR 寄存器值，设DLAB 位，设8Bit 数据位，1Bit 停止位，无校验。
P14 · p14_fig031116×647px
CH9438F (QFN-32(4x4)) — 3）、设置串口1 的波特率除数锁存器DLL 和DLM，串口1 为115200 波特率时，DLL 为0x83，DLM 为
3）、设置串口1 的波特率除数锁存器DLL 和DLM，串口1 为115200 波特率时，DLL 为0x83，DLM 为
P15 · p15_fig011905×1037px
CH9438F (QFN-32(4x4)) — SCS#
SCS#
P15 · p15_fig021720×999px
CH9438F (QFN-32(4x4)) — 11.3 读取串口数据 例1：CH9438 串口1 收到两字节数据0x11、0x22。 1）、设置FIFO 计数器控制器
11.3 读取串口数据 例1：CH9438 串口1 收到两字节数据0x11、0x22。 1）、设置FIFO 计数器控制器
P15 · p15_fig031116×646px
CH9438F (QFN-32(4x4)) — 11.3 读取串口数据 例1：CH9438 串口1 收到两字节数据0x11、0x22。 1）、设置FIFO 计数器控制器
11.3 读取串口数据 例1：CH9438 串口1 收到两字节数据0x11、0x22。 1）、设置FIFO 计数器控制器
P16 · p16_fig011928×966px
CH9438F (QFN-32(4x4)) — SCS#
SCS#
P16 · p16_fig021693×990px
CH9438F (QFN-32(4x4)) — 11.4 写串口数据 例1：CH9438 串口1 发送2 字节数据0xAA、0xBB 1）、设置FIFO 计数器控制器
11.4 写串口数据 例1：CH9438 串口1 发送2 字节数据0xAA、0xBB 1）、设置FIFO 计数器控制器
P16 · p16_fig031116×647px
CH9438F (QFN-32(4x4)) — 11.4 写串口数据 例1：CH9438 串口1 发送2 字节数据0xAA、0xBB 1）、设置FIFO 计数器控制器
11.4 写串口数据 例1：CH9438 串口1 发送2 字节数据0xAA、0xBB 1）、设置FIFO 计数器控制器

Technical Specifications & Part Details (CH9438F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9438F (QFN-32(4x4)) is a 32-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, SPI, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32(4x4))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, SPI, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9438F (QFN-32(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9438F (QFN-32(4x4))?

Manufactured by WCH, the CH9438F is housed in a QFN-32(4x4) package with 33 pins and a 0.40 mm lead pitch. Key pins include: 1 (PIN30 PIN29 、: Multiplexed I/O & Peripheral Pin PIN30 PIN29 、 (UART)), 2 (PIN10 PIN11 、: Multiplexed I/O & Peripheral Pin PIN10 PIN11 、 (UART)), 3 (PIN24 PIN19 、: Multiplexed I/O & Peripheral Pin PIN24 PIN19 、 (UART)), 4 (PIN16 PIN17 、: Multiplexed I/O & Peripheral Pin PIN16 PIN17 、 (UART)), 5 (PIN27 PIN28 、: Multiplexed I/O & Peripheral Pin PIN27 PIN28 、 (UART)), 6 (PIN23 PIN18 、: Multiplexed I/O & Peripheral Pin PIN23 PIN18 、 (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH9438F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9438F (QFN-32(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9438F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9438F (WCH, QFN-32(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & CH9438 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PIN30 PIN29 、Digital_IOSignal terminal PIN30 PIN29 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN30 PIN29 、. Supported peripheral buses: UART.
2PIN10 PIN11 、Digital_IOSignal terminal PIN10 PIN11 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN10 PIN11 、. Supported peripheral buses: UART.
3PIN24 PIN19 、Digital_IOSignal terminal PIN24 PIN19 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN24 PIN19 、. Supported peripheral buses: UART.
4PIN16 PIN17 、Digital_IOSignal terminal PIN16 PIN17 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN16 PIN17 、. Supported peripheral buses: UART.
5PIN27 PIN28 、Digital_IOSignal terminal PIN27 PIN28 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN27 PIN28 、. Supported peripheral buses: UART.
6PIN23 PIN18 、Digital_IOSignal terminal PIN23 PIN18 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN23 PIN18 、. Supported peripheral buses: UART.
7/GPIO7 RST#Digital_IOSignal terminal /GPIO7 RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General.
8/TNOW0Digital_IOSignal terminal /TNOW0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW0. Supported peripheral buses: General.
9/TNOW1 /GPIO1Digital_IOSignal terminal /TNOW1 /GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
10TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
11RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
12SCSDigital_IOSignal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: General.
13SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
14SDODigital_IOSignal terminal SDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO. Supported peripheral buses: General.
15SDIDigital_IOSignal terminal SDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI. Supported peripheral buses: General.
16TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
17RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
18RXD5Digital_IOSignal terminal RXD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD5. Supported peripheral buses: UART.
19RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
20TXD6Digital_IOSignal terminal TXD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD6. Supported peripheral buses: UART.
21RXD6Digital_IOSignal terminal RXD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD6. Supported peripheral buses: UART.
22/TNOW6Digital_IOSignal terminal /TNOW6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW6. Supported peripheral buses: General.
23TXD5Digital_IOSignal terminal TXD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD5. Supported peripheral buses: UART.
24TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
25TXD7Digital_IOSignal terminal TXD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD7. Supported peripheral buses: UART.
26RXD7Digital_IOSignal terminal RXD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD7. Supported peripheral buses: UART.
27TXD4Digital_IOSignal terminal TXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD4. Supported peripheral buses: UART.
28RXD4Digital_IOSignal terminal RXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD4. Supported peripheral buses: UART.
29RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
30TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
31VIODigital_IOSignal terminal VIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
32V CCDigital_IOSignal terminal V CC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V CC. Supported peripheral buses: General.
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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