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CH32F203C8T6 (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32F203C8T6

WCHID: C5341183LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32F203C8T6 (LQFP-48(7x7))1V_DDIO3_2OSC_IN3OSC_OUT4NRST5VDDA6PA0 WKUP -7PA18PA29PA310PA411PA512PA613PA714PB015PB116VSS1_17V_DDIO1_18PA819PA920PA1021PA1122PA1223PA1324PA1448VDD_VIO_347VSS_346PB945PB844BOOT043PB7/USB2DP42PB6/USB2DM41PB540PB439PB338PA1537PA14/SWCLK36VDD_235VSS_234PA13/SWDIO33PA12/USB1DP32VSS3_31PA1030PB729PB628PB527PB426PB325PA15Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1V_DDIO3_I/OMultiplexed I/O & Peripheral Pin V_DDIO3_ (General)
2OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
3OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
4NRSTISystem Enable & Hardware Reset (NRST)
5VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
6PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC, PWM)
7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
11PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI)
12PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
13PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
14PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
15PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
16VSS1_GNDGround Reference Pin (VSS1_)
17V_DDIO1_I/OMultiplexed I/O & Peripheral Pin V_DDIO1_ (General)
18PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
19PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
20PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
21PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, PWM, CAN)
22PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
23PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
24PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
25PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
26PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART)
27PB4I/OMultiplexed I/O & Peripheral Pin PB4 (UART)
28PB5I/OMultiplexed I/O & Peripheral Pin PB5 (I2C)
29PB6I/OMultiplexed I/O & Peripheral Pin PB6 (USB, I2C, PWM)
30PB7I/OMultiplexed I/O & Peripheral Pin PB7 (USB, I2C, PWM)
31PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
32VSS3_GNDGround Reference Pin (VSS3_)
33PA12/USB1DPI/OMultiplexed I/O & Peripheral Pin PA12/USB1DP (USB)
34PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
35VSS_2GNDGround Reference Pin (VSS_2)
36VDD_2PowerPower Supply Input (VDD_2 — 3.3V / 5.0V Standard Logic)
37PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
38PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
39PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
40PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
41PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
42PB6/USB2DMI/OMultiplexed I/O & Peripheral Pin PB6/USB2DM (USB)
43PB7/USB2DPI/OMultiplexed I/O & Peripheral Pin PB7/USB2DP (USB)
44BOOT0IInput-Only Pin BOOT0 (General)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
46PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
47VSS_3GNDGround Reference Pin (VSS_3)
48VDD_VIO_3PowerPower Supply Input (VDD_VIO_3 — 3.3V / 5.0V Standard Logic)
PIN 1 V_DDIO3_
I/O
Multiplexed I/O & Peripheral Pin V_DDIO3_ (General)
Design note: V_DDIO3_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32F203C8T6 (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32F203C8T6 (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32F203C8T6 (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32F203C8T6 (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32F203C8T6 (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32F203C8T6 (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32F203C8T6 (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH32F203
P1 · p01_fig01246×131px
CH32F203C8T6 (LQFP-48(7x7)) — 概述
概述
P13 · p13_fig011798×1147px
CH32F203C8T6 (LQFP-48(7x7)) — CH32F203K8T6
CH32F203K8T6
P13 · p13_fig02656×758px
CH32F203C8T6 (LQFP-48(7x7)) — PA7/ADC7 17
PA7/ADC7 17
P13 · p13_fig01P13
CH32F203C8T6 (LQFP-48(7x7)) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)

Technical Specifications & Part Details (CH32F203C8T6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32F203C8T6 (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32F203C8T6 (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32F203C8T6 (LQFP-48(7x7))?

Manufactured by WCH, the CH32F203C8T6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (V_DDIO3_: Multiplexed I/O & Peripheral Pin V_DDIO3_ (General)), 2 (OSC_IN: Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)), 3 (OSC_OUT: Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (VDDA: Power Supply Input (VDDA — 3.3V / 5.0V Standard Logic)), 6 (PA0 WKUP -: Multiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC, PWM)).

What are the IPC-7351B PCB Footprint dimensions for CH32F203C8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32F203C8T6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32F203C8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32F203C8T6 (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH32F203 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1V_DDIO3_Digital_IOSignal terminal V_DDIO3_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_DDIO3_. Supported peripheral buses: General.
2OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
3OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: UART, ADC, PWM.
7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
9PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
10PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
11PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI.
12PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
13PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
14PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: UART, ADC, PWM.
15PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
16VSS1_GND0V electrical ground return terminal (VSS1_) for internal core logic, I/O drivers, and analog sub-blocks.
17V_DDIO1_Digital_IOSignal terminal V_DDIO1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_DDIO1_. Supported peripheral buses: General.
18PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
19PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
20PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
21PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, PWM, CAN.
22PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
23PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
24PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
25PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
26PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: UART.
27PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: UART.
28PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SMBA. Supported peripheral buses: I2C.
29PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: USB, I2C, PWM.
30PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: USB, I2C, PWM.
31PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
32VSS3_GND0V electrical ground return terminal (VSS3_) for internal core logic, I/O drivers, and analog sub-blocks.
33PA12/USB1DPDigital_IOSignal terminal PA12/USB1DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/USB1DP. Supported peripheral buses: USB.
34PA13/SWDIODigital_IOSignal terminal PA13/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG.
35VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
36VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
38PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
39PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
40PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
41PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
42PB6/USB2DMDigital_IOSignal terminal PB6/USB2DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/USB2DM. Supported peripheral buses: USB.
43PB7/USB2DPDigital_IOSignal terminal PB7/USB2DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/USB2DP. Supported peripheral buses: USB.
44BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
45PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
46PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
47VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD_VIO_3Power_InPrimary positive power supply input (VDD_VIO_3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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