LQFP-48(7x7) · 48P
Synchronized Pinout (Symbol / 2D / 3D) (48/48)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PE2 | I/O | Multiplexed I/O & Peripheral Pin PE2 (General) |
| 2 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | NC | No Connect (Leave Floating) |
| 5 | PH0OSC IN (- PH0)_ | I/O | Multiplexed I/O & Peripheral Pin PH0OSC IN (- PH0)_ (I2C, RTC/CLK) |
| 6 | PH1OSC OUT - (PH1_) | I/O | Multiplexed I/O & Peripheral Pin PH1OSC OUT - (PH1_) (I2C, RTC/CLK) |
| 7 | NRST | I | System Enable & Hardware Reset (NRST) |
| 8 | VREF - | Analog | Multiplexed I/O & Peripheral Pin VREF - (General) |
| 9 | VREF+ | Analog | Multiplexed I/O & Peripheral Pin VREF+ (General) |
| 10 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC) |
| 11 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC) |
| 12 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, ADC) |
| 13 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (SPI, ADC) |
| 14 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (SPI, ADC, DAC) |
| 15 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC, DAC) |
| 16 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC) |
| 17 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC) |
| 18 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC) |
| 19 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (UART, SPI, ADC) |
| 20 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (SPI, RTC/CLK) |
| 21 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C) |
| 22 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| 23 | VSS | GND | Ground Reference Pin (VSS) |
| 24 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 25 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI) |
| 26 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C) |
| 27 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (UART, SPI) |
| 28 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (UART, SPI, PWM, RTC/CLK) |
| 29 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (USB, SPI, I2C, PWM, RTC/CLK) |
| 30 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (UART, SPI, I2C, RTC/CLK) |
| 31 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 32 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI, I2C) |
| 33 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI) |
| 34 | PA13(JTMS/ SWDIO) | I/O | Multiplexed I/O & Peripheral Pin PA13(JTMS/ SWDIO) (SWD/JTAG) |
| 35 | VSS | GND | Ground Reference Pin (VSS) |
| 36 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 37 | PA14(JTCK/ SWCLK) | I/O | Multiplexed I/O & Peripheral Pin PA14(JTCK/ SWCLK) (SWD/JTAG) |
| 38 | PA15(JTDI) | I/O | Multiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG) |
| 39 | PB3(JTDO/ TRACESWO) | I/O | Multiplexed I/O & Peripheral Pin PB3(JTDO/ TRACESWO) (SPI, I2C, SWD/JTAG) |
| 40 | PB4(NJTRST) | I/O | Multiplexed I/O & Peripheral Pin PB4(NJTRST) (UART, SPI, I2C, PWM, SWD/JTAG) |
| 41 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (UART, I2C, PWM) |
| 42 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART, I2C) |
| 43 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (UART, SPI, I2C) |
| 44 | PH2BOOT0 - | I/O | Multiplexed I/O & Peripheral Pin PH2BOOT0 - (RTC/CLK) |
| 45 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (SPI) |
| 46 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C) |
| 47 | VSS | GND | Ground Reference Pin (VSS) |
| 48 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
PIN 1 PE2
I/OMultiplexed I/O & Peripheral Pin PE2 (General)
Design note: Alt: TRACECLK LPTIM1 IN2 EVEN, TOUT_ ,
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32C542
P36 · p36_fig02EXACT PACKAGE
P110 · p110_fig01EXACT PACKAGE
P111 · p111_fig01EXACT PACKAGE
P112 · p112_fig01EXACT PACKAGE
P10 · p10_fig01938×1078px
P34 · p34_fig01809×539px
P34 · p34_fig02780×638px
P36 · p36_fig02P36
P49 · p49_fig011377×1137px
P49 · p49_fig01P49
P80 · p80_fig01921×756px
P80 · p80_fig021627×607px
Page 1 / 2 (14 extracted figures)
Technical Specifications & Part Details (STM32C542CCT6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32C542CCT6 (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, IrDA, DAC, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
2.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
144 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, IrDA, DAC, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH2BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol48 auto-grouped pins
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32C542 (2)
LQFP-64(10x10) · 64P
IPC-7351B
64P10.0×10.0×1.40mmP=0.5mm
STM32C542 (LQFP-64(10x10))
Mechanical Dimensions & Land Pattern (LQFP-48(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-48(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32C542CCT6 (LQFP-48(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32C542CCT6 (LQFP-48(7x7))?
Manufactured by ST, the STM32C542CCT6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN (- PH0)_: Multiplexed I/O & Peripheral Pin PH0OSC IN (- PH0)_ (I2C, RTC/CLK)), 6 (PH1OSC OUT - (PH1_): Multiplexed I/O & Peripheral Pin PH1OSC OUT - (PH1_) (I2C, RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32C542CCT6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32C542CCT6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32C542CCT6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32C542CCT6 (ST, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (48 pins) & STM32C542 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| 2 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | PH0OSC IN (- PH0)_ | Digital_IO | Signal terminal PH0OSC IN (- PH0)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDAEVENTOUT. Supported peripheral buses: I2C, RTC/CLK. |
| 6 | PH1OSC OUT - (PH1_) | Digital_IO | Signal terminal PH1OSC OUT - (PH1_) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCLEVENTOUT. Supported peripheral buses: I2C, RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VREF - | Analog | Signal terminal VREF - (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF -. Supported peripheral buses: General. |
| 9 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 10 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_, SPI1_RDY. Supported peripheral buses: UART, SPI, ADC. |
| 11 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC. |
| 12 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC. |
| 13 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: SPI, ADC. |
| 14 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, SPI1_NSS. Supported peripheral buses: SPI, ADC, DAC. |
| 15 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, DAC. |
| 16 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, SPI, ADC. |
| 17 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC. |
| 18 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: UART, SPI, ADC. |
| 19 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, SPI, ADC. |
| 20 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2EVENTOUT_. Supported peripheral buses: SPI, RTC/CLK. |
| 21 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL, SPI2SCK. Supported peripheral buses: UART, SPI, I2C. |
| 22 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| 23 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI. |
| 26 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C. |
| 27 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: UART, SPI. |
| 28 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI, PWM, RTC/CLK. |
| 29 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_. Supported peripheral buses: USB, SPI, I2C, PWM, RTC/CLK. |
| 30 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, RTC/CLK. |
| 31 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 32 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USB_DM. Supported peripheral buses: USB, UART, SPI, I2C. |
| 33 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USB_DP. Supported peripheral buses: USB, UART, SPI. |
| 34 | PA13(JTMS/ SWDIO) | Digital_IO | Signal terminal PA13(JTMS/ SWDIO) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13(JTMS/ SWDIO). Supported peripheral buses: SWD/JTAG. |
| 35 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 37 | PA14(JTCK/ SWCLK) | Digital_IO | Signal terminal PA14(JTCK/ SWCLK) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14(JTCK/ SWCLK). Supported peripheral buses: SWD/JTAG. |
| 38 | PA15(JTDI) | Digital_IO | Signal terminal PA15(JTDI) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| 39 | PB3(JTDO/ TRACESWO) | Digital_IO | Signal terminal PB3(JTDO/ TRACESWO) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_. Supported peripheral buses: SPI, I2C, SWD/JTAG. |
| 40 | PB4(NJTRST) | Digital_IO | Signal terminal PB4(NJTRST) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4(NJTRST). Supported peripheral buses: UART, SPI, I2C, PWM, SWD/JTAG. |
| 41 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: UART, I2C, PWM. |
| 42 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, I2C. |
| 43 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, SPI, I2C. |
| 44 | PH2BOOT0 - | Digital_IO | Signal terminal PH2BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH2BOOT0 -. Supported peripheral buses: RTC/CLK. |
| 45 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI. |
| 46 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, I2C. |
| 47 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |