Mechanical Dimensions & Land Pattern (QFN-20(3X3))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-20(3X3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH32V003F4U6 (QFN-20(3X3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH32V003F4U6 (QFN-20(3X3))?
Manufactured by WCH, the CH32V003F4U6 is housed in a QFN-20(3X3) package with 21 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7V~5.5V. Key pins include: 1 (PD4 I/O/A PD4: Multiplexed I/O & Peripheral Pin PD4 I/O/A PD4 (General)), 2 (PD5 I/O/A PD5: Multiplexed I/O & Peripheral Pin PD5 I/O/A PD5 (General)), 3 (PD6 I/O/A PD6: Multiplexed I/O & Peripheral Pin PD6 I/O/A PD6 (General)), 4 (PD7 I/O/A PD7: Multiplexed I/O & Peripheral Pin PD7 I/O/A PD7 (General)), 5 (PA1 I/O/A PA1: Multiplexed I/O & Peripheral Pin PA1 I/O/A PA1 (General)), 6 (PA2 I/O/A PA2: Multiplexed I/O & Peripheral Pin PA2 I/O/A PA2 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH32V003F4U6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V003F4U6 (QFN-20(3X3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.70 × 1.70 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V003F4U6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V003F4U6 (WCH, QFN-20(3X3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (21 pins) & CH32V003 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PD4 I/O/A PD4 | Digital_IO | Signal terminal PD4 I/O/A PD4 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD4 I/O/A PD4. Supported peripheral buses: General. |
| 2 | PD5 I/O/A PD5 | Digital_IO | Signal terminal PD5 I/O/A PD5 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD5 I/O/A PD5. Supported peripheral buses: General. |
| 3 | PD6 I/O/A PD6 | Digital_IO | Signal terminal PD6 I/O/A PD6 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD6 I/O/A PD6. Supported peripheral buses: General. |
| 4 | PD7 I/O/A PD7 | Digital_IO | Signal terminal PD7 I/O/A PD7 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD7 I/O/A PD7. Supported peripheral buses: General. |
| 5 | PA1 I/O/A PA1 | Digital_IO | Signal terminal PA1 I/O/A PA1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA1 I/O/A PA1. Supported peripheral buses: General. |
| 6 | PA2 I/O/A PA2 | Digital_IO | Signal terminal PA2 I/O/A PA2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA2 I/O/A PA2. Supported peripheral buses: General. |
| 7 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General. |
| 8 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General. |
| 9 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General. |
| 10 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General. |
| 11 | PC1 I/O/FT PC1 | Digital_IO | Signal terminal PC1 I/O/FT PC1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC1 I/O/FT PC1. Supported peripheral buses: SPI, I2C. |
| 12 | PC2 I/O/FT PC2 | Digital_IO | Signal terminal PC2 I/O/FT PC2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC2 I/O/FT PC2. Supported peripheral buses: I2C. |
| 13 | PC3 I/O PC3 | Digital_IO | Signal terminal PC3 I/O PC3 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC3 I/O PC3. Supported peripheral buses: General. |
| 14 | PC4 I/O/A PC4 | Digital_IO | Signal terminal PC4 I/O/A PC4 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC4 I/O/A PC4. Supported peripheral buses: RTC/CLK. |
| 15 | PC5 I/O/FT PC5 | Digital_IO | Signal terminal PC5 I/O/FT PC5 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC5 I/O/FT PC5. Supported peripheral buses: SPI. |
| 16 | PC6 I/O/FT PC6 | Digital_IO | Signal terminal PC6 I/O/FT PC6 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC6 I/O/FT PC6. Supported peripheral buses: SPI. |
| 17 | PC7 I/O PC7 | Digital_IO | Signal terminal PC7 I/O PC7 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC7 I/O PC7. Supported peripheral buses: SPI. |
| 18 | PD1 I/O/A PD1 | Digital_IO | Signal terminal PD1 I/O/A PD1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD1 I/O/A PD1. Supported peripheral buses: General. |
| 19 | PD2 I/O/A PD2 | Digital_IO | Signal terminal PD2 I/O/A PD2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD2 I/O/A PD2. Supported peripheral buses: General. |
| 20 | PD6 | Digital_IO | Signal terminal PD6 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General. |
| 21 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |