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STM32L010F4P6 (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L010F4P6

STTSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L010F4P6 (TSSOP-20)1PB9BOOT0 -2PC14OSC32 IN3PC15OSC32 OU4NRST5VDDA6PA0 CK IN -_7PA18PA29PA310PA420PA1419PA1318PA1017PA916VDD15VSS14PB113PA712PA611PA5Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PB9BOOT0 -I/OMultiplexed I/O & Peripheral Pin PB9BOOT0 - (General)
2PC14OSC32 IN -_I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)
3PC15OSC32 OUT -_I/OMultiplexed I/O & Peripheral Pin PC15OSC32 OUT -_ (RTC/CLK)
4NRSTISystem Enable & Hardware Reset (NRST)
5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
6PA0 CK IN -_I/OMultiplexed I/O & Peripheral Pin PA0 CK IN -_ (UART, ADC, PWM, RTC/CLK)
7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, RTC/CLK)
9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
11PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
12PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
13PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, ADC)
14PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
15VSSGNDGround Reference Pin (VSS)
16VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
17PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)
18PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM, RTC/CLK)
19PA13I/OMultiplexed I/O & Peripheral Pin PA13 (I2C, SWD/JTAG)
20PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SPI, I2C, SWD/JTAG)
PIN 1 PB9BOOT0 -
I/O
Multiplexed I/O & Peripheral Pin PB9BOOT0 - (General)
Design note: Signal terminal PB9BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9BOOT0 -. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
STM32L010F4P6 (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L010F4P6 (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L010F4P6 (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L010F4P6 (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L010F4P6 (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L010F4P6 (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for STM32L010
P29 · p29_fig01EXACT PACKAGE
STM32L010F4P6 (TSSOP-20) — Figure 3. STM32L010F4/K4 TSSOP20 pinout
Figure 3. STM32L010F4/K4 TSSOP20 pinout
P29 · p29_fig02EXACT PACKAGE
STM32L010F4P6 (TSSOP-20) — PA7
PA7
P82 · p82_fig01EXACT PACKAGE
STM32L010F4P6 (TSSOP-20) — Figure 28. TSSOP20 - 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
Figure 28. TSSOP20 - 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
P83 · p83_fig01EXACT PACKAGE
STM32L010F4P6 (TSSOP-20) — Figure 29. TSSOP20 - 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
Figure 29. TSSOP20 - 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
P84 · p84_fig01EXACT PACKAGE
STM32L010F4P6 (TSSOP-20) — Figure 30. TSSOP20 marking example (package top view)
Figure 30. TSSOP20 marking example (package top view)
P84 · p84_fig02EXACT PACKAGE
STM32L010F4P6 (TSSOP-20) — Figure 30. TSSOP20 marking example (package top view)
Figure 30. TSSOP20 marking example (package top view)
P1 · p01_fig01881×427px
STM32L010F4P6 (TSSOP-20) — • 4x peripherals communication interface
• 4x peripherals communication interface
P29 · p29_fig01P29
STM32L010F4P6 (TSSOP-20) — Datasheet Page 29 (p29_fig01)
Datasheet Page 29 (p29_fig01)
P37 · p37_fig011546×1132px
STM32L010F4P6 (TSSOP-20) — Figure 7. Power supply scheme
Figure 7. Power supply scheme
P37 · p37_fig021546×586px
STM32L010F4P6 (TSSOP-20) — Figure 8. Current consumption measurement scheme
Figure 8. Current consumption measurement scheme
P37 · p37_fig01P37
STM32L010F4P6 (TSSOP-20) — Datasheet Page 37 (p37_fig01)
Datasheet Page 37 (p37_fig01)
P75 · p75_fig011546×701px
STM32L010F4P6 (TSSOP-20) — Figure 24. Typical connection diagram using the ADC
Figure 24. Typical connection diagram using the ADC
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (STM32L010F4P6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L010F4P6 (TSSOP-20) is a 20-pin embedded microcontroller unit (mcu) featuring a 6.50 × 4.40 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.20 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB9BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32L010 (6)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L010F4P6 (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L010F4P6 (TSSOP-20)?

Manufactured by ST, the STM32L010F4P6 is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.8 V to 3.6 V. Key pins include: 1 (PB9BOOT0 -: Multiplexed I/O & Peripheral Pin PB9BOOT0 - (General)), 2 (PC14OSC32 IN -_: Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)), 3 (PC15OSC32 OUT -_: Multiplexed I/O & Peripheral Pin PC15OSC32 OUT -_ (RTC/CLK)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), 6 (PA0 CK IN -_: Multiplexed I/O & Peripheral Pin PA0 CK IN -_ (UART, ADC, PWM, RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32L010F4P6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L010F4P6 (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L010F4P6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L010F4P6 (ST, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & STM32L010 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PB9BOOT0 -Digital_IOSignal terminal PB9BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9BOOT0 -. Supported peripheral buses: General.
2PC14OSC32 IN -_Digital_IOSignal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK.
3PC15OSC32 OUT -_Digital_IOSignal terminal PC15OSC32 OUT -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15OSC32 OUT -_. Supported peripheral buses: RTC/CLK.
4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6PA0 CK IN -_Digital_IOSignal terminal PA0 CK IN -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0 CK IN -_. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, RTC/CLK.
9PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC.
10PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSLPTIM1IN1. Supported peripheral buses: UART, SPI, ADC.
11PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCKLPTIM1IN2. Supported peripheral buses: SPI, ADC.
12PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISOLPTIM1ETR. Supported peripheral buses: UART, SPI, ADC.
13PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSILPTIM1OUT. Supported peripheral buses: UART, SPI, ADC.
14PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
15VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
16VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
17PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, RTC/CLK.
18PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM, RTC/CLK.
19PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: I2C, SWD/JTAG.
20PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISOLPUART1TX. Supported peripheral buses: SPI, I2C, SWD/JTAG.
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