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C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) — Symbol, Footprint IPC-7351B & 3D STEP Model

C529058

SemiconductorLQFP-100_L14.0-W14.0-P0.50-LS16.0-BL · 100 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL)1PE22PE33PE44PE55PE66VBAT7PC138PC14-OSC32_I9PC15-OSC32_O10VSS11VDD12PH0-OSC_IN13PH1-OSC_OUT14NRST15PC016PC117PC2_C18PC3_C19VSSA20VREF+21VDDA22PA023PA124PA225PA326VSS27VDD28PA429PA530PA631PA732PC433PC534PB035PB136PB237PE738PE839PE940PE1041PE1142PE1243PE1344PE1445PE1546PB1047PB1148VCAP49VSS50VDD100VDD99VSS98PE197PE096PB995PB894BOOT093PB792PB691PB590PB489PB388PD787PD686PD585PD484PD383PD282PD181PD080PC1279PC1178PC1077PA1576PA1475VDD74VSS73VCAP72PA1371PA1270PA1169PA1068PA967PA866PC965PC864PC763PC662PD1561PD1460PD1359PD1258PD1157PD1056PD955PD854PB1553PB1452PB1351PB12Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.268.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=14.00mm · Pitch e=0.50mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
4PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
5PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
6VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
7PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
8PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
9PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
10VSSGNDGround Reference Pin (VSS)
11VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
12PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
13PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
14NRSTISystem Enable & Hardware Reset (NRST)
15PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
16PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
17PC2_CI/OMultiplexed I/O & Peripheral Pin PC2_C (General)
18PC3_CI/OMultiplexed I/O & Peripheral Pin PC3_C (General)
19VSSAGNDGround Reference Pin (VSSA)
20VREF+I/OMultiplexed I/O & Peripheral Pin VREF+ (General)
21VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
22PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
23PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
24PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
25PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
26VSSGNDGround Reference Pin (VSS)
27VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
28PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
29PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
30PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
31PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
32PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
33PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
34PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
35PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
36PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
37PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
38PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
39PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
40PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
41PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
42PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
43PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
44PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
45PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
46PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
47PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
48VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
49VSSGNDExposed Thermal & Ground Pad (VSS)
50VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
51PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
52PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
53PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
54PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
55PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
56PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
57PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
58PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
59PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
60PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
61PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
62PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
63PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
64PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
65PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
66PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
67PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
68PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
69PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
70PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
71PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
72PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
73VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
74VSSGNDGround Reference Pin (VSS)
75VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
76PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
77PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
78PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
79PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
80PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
81PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
82PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
83PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
84PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
85PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
86PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
87PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
88PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
89PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
90PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
91PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
92PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
93PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
94BOOT0IInput-Only Pin BOOT0 (General)
95PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
96PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
97PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
98PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
99VSSGNDGround Reference Pin (VSS)
100VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
PIN 1 PE2
I/O
Multiplexed I/O & Peripheral Pin PE2 (General)
Design note: Signal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C529058 (Semiconductor · LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) - 4. Package Dimensions (D×E×A)
LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C529058)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) is a 100-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL)?

Manufactured by Semiconductor, the C529058 is housed in a LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), 6 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for C529058?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C529058 (LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C529058?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C529058 (Semiconductor, LQFP-100_L14.0-W14.0-P0.50-LS16.0-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32H743 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
4PE5Digital_IOSignal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
5PE6Digital_IOSignal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
6VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7PC13Digital_IOSignal terminal PC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
8PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
9PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
13PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
14NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
15PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
16PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
17PC2_CDigital_IOSignal terminal PC2_C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2_C. Supported peripheral buses: General.
18PC3_CDigital_IOSignal terminal PC3_C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3_C. Supported peripheral buses: General.
19VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
20VREF+Digital_IOSignal terminal VREF+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
21VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
23PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
24PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
25PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
26VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
27VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
29PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
30PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
31PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
32PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
33PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
34PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
35PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
36PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
37PE7Digital_IOSignal terminal PE7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
38PE8Digital_IOSignal terminal PE8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
39PE9Digital_IOSignal terminal PE9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General.
40PE10Digital_IOSignal terminal PE10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
41PE11Digital_IOSignal terminal PE11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General.
42PE12Digital_IOSignal terminal PE12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE12. Supported peripheral buses: General.
43PE13Digital_IOSignal terminal PE13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE13. Supported peripheral buses: General.
44PE14Digital_IOSignal terminal PE14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General.
45PE15Digital_IOSignal terminal PE15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE15. Supported peripheral buses: General.
46PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
47PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
48VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
49VSSGNDBottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
51PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
52PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
53PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
54PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
55PD8Digital_IOSignal terminal PD8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
56PD9Digital_IOSignal terminal PD9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
57PD10Digital_IOSignal terminal PD10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
58PD11Digital_IOSignal terminal PD11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
59PD12Digital_IOSignal terminal PD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
60PD13Digital_IOSignal terminal PD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
61PD14Digital_IOSignal terminal PD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
62PD15Digital_IOSignal terminal PD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
63PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
64PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
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