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CH484M (QFN-42(3.5x9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH484M

WCHID: C5280970QFN-42(3.5x9) · 43 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH484M (QFN-42(3.5x9))1AS1 AS0 ,2A0X A0Y ,3A0X A0Y ,4A1X A1Y ,5A1X A1Y ,6A2X A2Y ,7A2X A2Y ,8A3X A3Y ,9A3X A3Y ,10SSBX11B0X B0Y ,12B0X B0Y ,13SEL014VDD15GND16NC17NC18NC19EN#20BX BY ,21BX BY ,22BS1 BS0 ,43GND42NC41NC40NC39GND38SSA0X37SSA0Y36SSB0X35SSB0Y34SSA1X33SSA1Y32SSB1X31SSB1Y30GND29SSA2X28AS1 AS0 ,27AX AY ,26AX AY ,25BS1 BS0 ,24VDD23SSB3XGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.233.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243E=3.50mm · Pitch e=0.50mmD=9.00mm-4-3-2-10123476543210-1-2-3-4-5-6-7mm
3. 3D CAD MODEL
Package Body: 3.50mm × 9.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (43/43)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1AS1 AS0 ,I/OMultiplexed I/O & Peripheral Pin AS1 AS0 , (General)
2A0X A0Y ,I/OMultiplexed I/O & Peripheral Pin A0X A0Y , (General)
3A0X A0Y ,I/OMultiplexed I/O & Peripheral Pin A0X A0Y , (General)
4A1X A1Y ,I/OMultiplexed I/O & Peripheral Pin A1X A1Y , (General)
5A1X A1Y ,I/OMultiplexed I/O & Peripheral Pin A1X A1Y , (General)
6A2X A2Y ,I/OMultiplexed I/O & Peripheral Pin A2X A2Y , (General)
7A2X A2Y ,I/OMultiplexed I/O & Peripheral Pin A2X A2Y , (General)
8A3X A3Y ,I/OMultiplexed I/O & Peripheral Pin A3X A3Y , (General)
9A3X A3Y ,I/OMultiplexed I/O & Peripheral Pin A3X A3Y , (General)
10SSBXI/OMultiplexed I/O & Peripheral Pin SSBX (General)
11B0X B0Y ,I/OMultiplexed I/O & Peripheral Pin B0X B0Y , (General)
12B0X B0Y ,I/OMultiplexed I/O & Peripheral Pin B0X B0Y , (General)
13SEL0I/OMultiplexed I/O & Peripheral Pin SEL0 (General)
14VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
15GNDGNDGround Reference Pin (GND)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18NCI/OMultiplexed I/O & Peripheral Pin NC (General)
19EN#I/OMultiplexed I/O & Peripheral Pin EN# (General)
20BX BY ,I/OMultiplexed I/O & Peripheral Pin BX BY , (General)
21BX BY ,I/OMultiplexed I/O & Peripheral Pin BX BY , (General)
22BS1 BS0 ,I/OMultiplexed I/O & Peripheral Pin BS1 BS0 , (General)
23SSB3XI/OMultiplexed I/O & Peripheral Pin SSB3X (General)
24VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
25BS1 BS0 ,I/OMultiplexed I/O & Peripheral Pin BS1 BS0 , (General)
26AX AY ,I/OMultiplexed I/O & Peripheral Pin AX AY , (General)
27AX AY ,I/OMultiplexed I/O & Peripheral Pin AX AY , (General)
28AS1 AS0 ,I/OMultiplexed I/O & Peripheral Pin AS1 AS0 , (General)
29SSA2XI/OMultiplexed I/O & Peripheral Pin SSA2X (General)
30GNDGNDGround Reference Pin (GND)
31SSB1YI/OMultiplexed I/O & Peripheral Pin SSB1Y (General)
32SSB1XI/OMultiplexed I/O & Peripheral Pin SSB1X (General)
33SSA1YI/OMultiplexed I/O & Peripheral Pin SSA1Y (General)
34SSA1XI/OMultiplexed I/O & Peripheral Pin SSA1X (General)
35SSB0YI/OMultiplexed I/O & Peripheral Pin SSB0Y (General)
36SSB0XI/OMultiplexed I/O & Peripheral Pin SSB0X (General)
37SSA0YI/OMultiplexed I/O & Peripheral Pin SSA0Y (General)
38SSA0XI/OMultiplexed I/O & Peripheral Pin SSA0X (General)
39GNDGNDExposed Thermal & Ground Pad (GND)
40NCI/OMultiplexed I/O & Peripheral Pin NC (General)
41NCI/OMultiplexed I/O & Peripheral Pin NC (General)
42NCI/OMultiplexed I/O & Peripheral Pin NC (General)
43GNDGNDGround Reference Pin (GND)
PIN 1 AS1 AS0 ,
I/O
Multiplexed I/O & Peripheral Pin AS1 AS0 , (General)
Design note: Channel A one-of -four analog switch selection input: 00:Select0#(A0*) . 01:Select1#(A1*) . 10:Select2#(A2*) . 11:Select3#(A3*) .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH484M (WCH · QFN-42(3.5x9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH484M (QFN-42(3.5x9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH484M (QFN-42(3.5x9)) - 2. Standard Pinout (Top View)
True package pinout (43 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH484M (QFN-42(3.5x9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH484M (QFN-42(3.5x9)) - 4. Package Dimensions (D×E×A)
QFN-42(3.5x9) · 3.50×9.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH484M (QFN-42(3.5x9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (43 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH484M (QFN-42(3.5x9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH484 / CH486
P2 · p02_fig011732×1691px
CH484M (QFN-42(3.5x9)) — GND 19 | SSB1 X 12 | SSB1 Y 11 | VDD 9 | GND 10 | SSBY 7 SSBX 6 | SSA0 Y 17 | SSB0 X 16 | GND 0 | EN# 1 | SEL 8 | GND 4 | SSAX 2 | VDD 5 SSB0 Y 15 SSAY 3 | SSA1 Y 13 SSA1 X 14 | SSA0 X 18 | VDD 20 | SEL=0 SEL=1 | A | B | o | CH482D | NC. 39
GND 19 | SSB1 X 12 | SSB1 Y 11 | VDD 9 | GND 10 | SSBY 7 SSBX 6 | SSA0 Y 17 | SSB0 X 16 | GND 0 | EN# 1 | SEL 8 | GND 4 | SSAX 2 | VDD 5 SSB0 Y 15 SSAY 3 | SSA1 Y 13 SSA1 X 14 | SSA0 X 18 | VDD 20 | SEL=0 SEL=1 | A | B | o | CH482D | NC. 39
P3 · p03_fig01666×645px
CH484M (QFN-42(3.5x9)) — Package Body size Lead pitch Description Part No.
Package Body size Lead pitch Description Part No.
P3 · p03_fig01P3
CH484M (QFN-42(3.5x9)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P19 · p19_fig01All Packages in PDF
CH484M (QFN-42(3.5x9)) — Note: All dimensions are in millimeters. The pin center spacing is a nominal value, and the error of other dimensions is not greater than ±0.2mm. 8.1. QFN20-2.5X4.5 8.2. QFN28-4X4
Note: All dimensions are in millimeters. The pin center spacing is a nominal value, and the error of other dimensions is not greater than ±0.2mm. 8.1. QFN20-2.5X4.5 8.2. QFN28-4X4
P19 · p19_fig02All Packages in PDF
CH484M (QFN-42(3.5x9)) — Note: All dimensions are in millimeters. The pin center spacing is a nominal value, and the error of other dimensions is not greater than ±0.2mm. 8.1. QFN20-2.5X4.5 8.2. QFN28-4X4
Note: All dimensions are in millimeters. The pin center spacing is a nominal value, and the error of other dimensions is not greater than ±0.2mm. 8.1. QFN20-2.5X4.5 8.2. QFN28-4X4

Technical Specifications & Part Details (CH484M)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH484M (QFN-42(3.5x9)) is a 42-pin standard electronic & interconnect component featuring a 9.00 × 3.50 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 3.50 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-42(3.5x9))
Pin Count & Lead PitchN / e
42 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol43 auto-grouped pins
OK
IPC-7351B Land Pattern43 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.10×7.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH484 / CH486 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-42(3.5x9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 3.50 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.79 mm
Pins / Total PadsTopology
43P / 43Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-42(3.5x9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH484M (QFN-42(3.5x9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH484M (QFN-42(3.5x9))?

Manufactured by WCH, the CH484M is housed in a QFN-42(3.5x9) package with 43 pins and a 0.50 mm lead pitch. Key pins include: 1 (AS1 AS0 ,: Multiplexed I/O & Peripheral Pin AS1 AS0 , (General)), 2 (A0X A0Y ,: Multiplexed I/O & Peripheral Pin A0X A0Y , (General)), 3 (A0X A0Y ,: Multiplexed I/O & Peripheral Pin A0X A0Y , (General)), 4 (A1X A1Y ,: Multiplexed I/O & Peripheral Pin A1X A1Y , (General)), 5 (A1X A1Y ,: Multiplexed I/O & Peripheral Pin A1X A1Y , (General)), 6 (A2X A2Y ,: Multiplexed I/O & Peripheral Pin A2X A2Y , (General)).

What are the IPC-7351B PCB Footprint dimensions for CH484M?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH484M (QFN-42(3.5x9)) has a nominal body envelope of 3.50 × 9.00 mm, pitch e = 0.50 mm, and 43 copper pads plus a central exposed thermal pad (EPAD) of 2.10 × 7.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH484M?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH484M (WCH, QFN-42(3.5x9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (43 pins) & CH484 / CH486 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1AS1 AS0 ,Digital_IOSignal terminal AS1 AS0 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AS1 AS0 ,. Supported peripheral buses: General.
2A0X A0Y ,Digital_IOSignal terminal A0X A0Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0X A0Y ,. Supported peripheral buses: General.
3A0X A0Y ,Digital_IOSignal terminal A0X A0Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0X A0Y ,. Supported peripheral buses: General.
4A1X A1Y ,Digital_IOSignal terminal A1X A1Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1X A1Y ,. Supported peripheral buses: General.
5A1X A1Y ,Digital_IOSignal terminal A1X A1Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1X A1Y ,. Supported peripheral buses: General.
6A2X A2Y ,Digital_IOSignal terminal A2X A2Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2X A2Y ,. Supported peripheral buses: General.
7A2X A2Y ,Digital_IOSignal terminal A2X A2Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2X A2Y ,. Supported peripheral buses: General.
8A3X A3Y ,Digital_IOSignal terminal A3X A3Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3X A3Y ,. Supported peripheral buses: General.
9A3X A3Y ,Digital_IOSignal terminal A3X A3Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3X A3Y ,. Supported peripheral buses: General.
10SSBXDigital_IOSignal terminal SSBX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSBX. Supported peripheral buses: General.
11B0X B0Y ,Digital_IOSignal terminal B0X B0Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B0X B0Y ,. Supported peripheral buses: General.
12B0X B0Y ,Digital_IOSignal terminal B0X B0Y , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B0X B0Y ,. Supported peripheral buses: General.
13SEL0Digital_IOSignal terminal SEL0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL0. Supported peripheral buses: General.
14VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
16NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
19EN#Digital_IOSignal terminal EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EN#. Supported peripheral buses: General.
20BX BY ,Digital_IOSignal terminal BX BY , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BX BY ,. Supported peripheral buses: General.
21BX BY ,Digital_IOSignal terminal BX BY , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BX BY ,. Supported peripheral buses: General.
22BS1 BS0 ,Digital_IOSignal terminal BS1 BS0 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BS1 BS0 ,. Supported peripheral buses: General.
23SSB3XDigital_IOSignal terminal SSB3X (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSB3X. Supported peripheral buses: General.
24VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25BS1 BS0 ,Digital_IOSignal terminal BS1 BS0 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BS1 BS0 ,. Supported peripheral buses: General.
26AX AY ,Digital_IOSignal terminal AX AY , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AX AY ,. Supported peripheral buses: General.
27AX AY ,Digital_IOSignal terminal AX AY , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AX AY ,. Supported peripheral buses: General.
28AS1 AS0 ,Digital_IOSignal terminal AS1 AS0 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AS1 AS0 ,. Supported peripheral buses: General.
29SSA2XDigital_IOSignal terminal SSA2X (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSA2X. Supported peripheral buses: General.
30GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
31SSB1YDigital_IOSignal terminal SSB1Y (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSB1Y. Supported peripheral buses: General.
32SSB1XDigital_IOSignal terminal SSB1X (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSB1X. Supported peripheral buses: General.
33SSA1YDigital_IOSignal terminal SSA1Y (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSA1Y. Supported peripheral buses: General.
34SSA1XDigital_IOSignal terminal SSA1X (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSA1X. Supported peripheral buses: General.
35SSB0YDigital_IOSignal terminal SSB0Y (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSB0Y. Supported peripheral buses: General.
36SSB0XDigital_IOSignal terminal SSB0X (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSB0X. Supported peripheral buses: General.
37SSA0YDigital_IOSignal terminal SSA0Y (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSA0Y. Supported peripheral buses: General.
38SSA0XDigital_IOSignal terminal SSA0X (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSA0X. Supported peripheral buses: General.
39GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
40NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
41NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
42NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
43GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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