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STM32H755ZIT3 (LQFP-144(20x20)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H755ZIT3

STID: C5271088LQFP-144(20x20) · 144 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H755ZIT3 (LQFP-144(20x20))1PE22PE33PE44PE55PE66VSS7VDD8VBAT9PC1310PC14-OSC32_I11PC15-OSC32_O12VSS13VDD14VSSSMPS15VLXSMPS16VDDSMPS17VFBSMPS18VSS19VDD20PF621PF722PF823PF924PF1025PH0-OSC_IN26PH1-OSC_OUT27NRST28PC029PC130PC2_C31PC3_C32VDD33VSS34VSSA35VREF+36VDDA37PA038PA139PA240PA341VSS42VDD43PA444PA545PA646PA747PC448PC549PB050PB151PB252PF1153PF1454PF1555VSS56VDD57PE758PE859PE960PE1061PE1162PE1263PE1364PE1465PE1566PB1067PB1168VCAP69VSS70VDDLDO71VDD72PB12144VDD143VDDLDO142PDR_ON141VSS140VCAP139PE1138PE0137PB9136PB8135BOOT0134PB7133PB6132PB5131PB4130PB3129VDD128VSS127PG14126PG13125PG12124PG11123PG10122PG9121PD7120PD6119VDD118VSS117PD5116PD4115PD3114PD2113PD1112PD0111PC12110PC11109PC10108PA15107PA14106VDD105VDDLDO104VSS103VCAP102PA13101PA12100PA1199PA1098PA997PA896PC995PC894PC793PC692VDD91VDD33USB90VDD50USB89VSS88PG887PG786PG685PD1584PD1483PD1382PD1281PD1180VSS79VDD78PD1077PD976PD875PB1574PB1473PB13Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.896.591.486.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4-91.4-96.5mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144E=20.00mm · Pitch e=0.50mmD=20.00mm-17-15-13-11-9-7-5-3-113579111315171715131197531-1-3-5-7-9-11-13-15-17mm
3. 3D CAD MODEL
Package Body: 20.00mm × 20.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
4PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
5PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
6VSSGNDGround Reference Pin (VSS)
7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
8VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
9PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
10PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
11PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
12VSSGNDGround Reference Pin (VSS)
13VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
14VSSSMPSGNDGround Reference Pin (VSSSMPS)
15VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
16VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
17VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
18VSSGNDGround Reference Pin (VSS)
19VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
20PF6I/OMultiplexed I/O & Peripheral Pin PF6 (General)
21PF7I/OMultiplexed I/O & Peripheral Pin PF7 (General)
22PF8I/OMultiplexed I/O & Peripheral Pin PF8 (General)
23PF9I/OMultiplexed I/O & Peripheral Pin PF9 (General)
24PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
25PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
26PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
27NRSTISystem Enable & Hardware Reset (NRST)
28PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
29PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
30PC2_CI/OMultiplexed I/O & Peripheral Pin PC2_C (General)
31PC3_CI/OMultiplexed I/O & Peripheral Pin PC3_C (General)
32VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
33VSSGNDGround Reference Pin (VSS)
34VSSAGNDGround Reference Pin (VSSA)
35VREF+I/OMultiplexed I/O & Peripheral Pin VREF+ (General)
36VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
37PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
38PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
39PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
40PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
41VSSGNDGround Reference Pin (VSS)
42VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
43PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
44PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
45PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
46PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
47PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
48PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
49PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
50PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
51PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
52PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
53PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
54PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
55VSSGNDGround Reference Pin (VSS)
56VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
57PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
58PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
59PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
60PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
61PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
62PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
63PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
64PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
65PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
66PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
67PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
68VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
69VSSGNDGround Reference Pin (VSS)
70VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
71VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
72PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
73PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
74PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
75PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
76PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
77PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
78PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
79VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
80VSSGNDGround Reference Pin (VSS)
81PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
82PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
83PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
84PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
85PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
86PG6I/OMultiplexed I/O & Peripheral Pin PG6 (General)
87PG7I/OMultiplexed I/O & Peripheral Pin PG7 (General)
88PG8I/OMultiplexed I/O & Peripheral Pin PG8 (General)
89VSSGNDGround Reference Pin (VSS)
90VDD50USBPowerPower Supply Input (VDD50USB — 3.3V VDD (Max 4.0V))
91VDD33USBPowerPower Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))
92VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
93PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
94PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
95PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
96PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
97PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
98PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
99PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
100PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
101PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
102PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
103VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
104VSSGNDGround Reference Pin (VSS)
105VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
106VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
107PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
108PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
109PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
110PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
111PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
112PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
113PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
114PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
115PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
116PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
117PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
118VSSGNDGround Reference Pin (VSS)
119VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
120PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
121PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
122PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
123PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
124PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
125PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
126PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
127PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
128VSSGNDGround Reference Pin (VSS)
129VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
130PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
131PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
132PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
133PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
134PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
135BOOT0IInput-Only Pin BOOT0 (General)
136PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
137PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
138PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
139PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
140VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
141VSSGNDGround Reference Pin (VSS)
142PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
143VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
144VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN 1 PE2
I/O
Multiplexed I/O & Peripheral Pin PE2 (General)
Design note: Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H755ZIT3 (ST · LQFP-144(20x20))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H755ZIT3 (LQFP-144(20x20)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H755ZIT3 (LQFP-144(20x20)) - 2. Standard Pinout (Top View)
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H755ZIT3 (LQFP-144(20x20)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H755ZIT3 (LQFP-144(20x20)) - 4. Package Dimensions (D×E×A)
LQFP-144(20x20) · 20.00×20.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H755ZIT3 (LQFP-144(20x20)) - 5. Recommended Land Pattern
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H755ZIT3 (LQFP-144(20x20)) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (STM32H755ZIT3)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H755ZIT3 (LQFP-144(20x20)) is a 144-pin embedded microcontroller unit (mcu) featuring a 20.00 × 20.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
20.00 × 20.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-144(20x20))
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol144 auto-grouped pins
OK
IPC-7351B Land Pattern144 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-144(20x20))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-144(20x20)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H755ZIT3 (LQFP-144(20x20))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H755ZIT3 (LQFP-144(20x20))?

Manufactured by ST, the STM32H755ZIT3 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for STM32H755ZIT3?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H755ZIT3 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H755ZIT3?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H755ZIT3 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32H755 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
4PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
5PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
8VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
9PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
10PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
11PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
15VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
16VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
17VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
18VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
20PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: General.
21PF7Digital_IOSignal terminal PF7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: General.
22PF8Digital_IOSignal terminal PF8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF8. Supported peripheral buses: General.
23PF9Digital_IOSignal terminal PF9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF9. Supported peripheral buses: General.
24PF10Digital_IOSignal terminal PF10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General.
25PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
26PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
27NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
28PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
29PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
30PC2_CDigital_IOSignal terminal PC2_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2_C. Supported peripheral buses: General.
31PC3_CDigital_IOSignal terminal PC3_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3_C. Supported peripheral buses: General.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
34VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
35VREF+Digital_IOSignal terminal VREF+ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
36VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
37PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
38PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
39PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
40PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
41VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
42VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
43PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
44PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
45PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
46PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
47PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
48PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
49PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
50PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
51PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
52PF11Digital_IOSignal terminal PF11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF11. Supported peripheral buses: General.
53PF14Digital_IOSignal terminal PF14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General.
54PF15Digital_IOSignal terminal PF15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF15. Supported peripheral buses: General.
55VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
56VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
57PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
58PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
59PE9Digital_IOSignal terminal PE9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General.
60PE10Digital_IOSignal terminal PE10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
61PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General.
62PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: General.
63PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: General.
64PE14Digital_IOSignal terminal PE14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General.
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