STM32U575CIT6Q (LQFP-48(7x7)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32U575CIT6Q (LQFP-48(7x7))?

Manufactured by ST, the STM32U575CIT6Q is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN -_ (PH0): Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)), 6 (PH1OSC OUT -_ (PH1): Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32U575CIT6Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U575CIT6Q (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U575CIT6Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U575CIT6Q (ST, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VBAT	Power	Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2	PC13	I/O	Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3	PC14 - OSC32_IN (PC14)	I/O	Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
4	NC	NC	No Connect (Leave Floating)
5	PH0OSC IN -_ (PH0)	I/O	Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
6	PH1OSC OUT -_ (PH1)	I/O	Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)
7	NRST	I	System Enable & Hardware Reset (NRST)
8	VSSA	GND	Ground Reference Pin (VSSA)
9	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
10	PA0	I/O	Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
11	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, SPI, ADC, PWM)
12	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
13	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
14	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
15	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC, DAC, PWM)
16	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
17	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, I2C, ADC, PWM)
18	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (SPI, ADC, PWM)
19	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
20	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (I2C, ADC, RTC/CLK)
21	P21	I/O	Multiplexed I/O & Peripheral Pin P21 (General)
22	P22	I/O	Multiplexed I/O & Peripheral Pin P22 (General)
23	P23	I/O	Multiplexed I/O & Peripheral Pin P23 (General)
24	P24	I/O	Multiplexed I/O & Peripheral Pin P24 (General)
25	P25	I/O	Multiplexed I/O & Peripheral Pin P25 (General)
26	P26	I/O	Multiplexed I/O & Peripheral Pin P26 (General)
27	P27	I/O	Multiplexed I/O & Peripheral Pin P27 (General)
28	P28	I/O	Multiplexed I/O & Peripheral Pin P28 (General)
29	P29	I/O	Multiplexed I/O & Peripheral Pin P29 (General)
30	P30	I/O	Multiplexed I/O & Peripheral Pin P30 (General)
31	P31	I/O	Multiplexed I/O & Peripheral Pin P31 (General)
32	P32	I/O	Multiplexed I/O & Peripheral Pin P32 (General)
33	P33	I/O	Multiplexed I/O & Peripheral Pin P33 (General)
34	P34	I/O	Multiplexed I/O & Peripheral Pin P34 (General)
35	P35	I/O	Multiplexed I/O & Peripheral Pin P35 (General)
36	P36	I/O	Multiplexed I/O & Peripheral Pin P36 (General)
37	P37	I/O	Multiplexed I/O & Peripheral Pin P37 (General)
38	P38	I/O	Multiplexed I/O & Peripheral Pin P38 (General)
39	P39	I/O	Multiplexed I/O & Peripheral Pin P39 (General)
40	P40	I/O	Multiplexed I/O & Peripheral Pin P40 (General)
41	P41	I/O	Multiplexed I/O & Peripheral Pin P41 (General)
42	P42	I/O	Multiplexed I/O & Peripheral Pin P42 (General)
43	P43	I/O	Multiplexed I/O & Peripheral Pin P43 (General)
44	P44	I/O	Multiplexed I/O & Peripheral Pin P44 (General)
45	P45	I/O	Multiplexed I/O & Peripheral Pin P45 (General)
46	P46	I/O	Multiplexed I/O & Peripheral Pin P46 (General)
47	P47	I/O	Multiplexed I/O & Peripheral Pin P47 (General)
48	P48	I/O	Multiplexed I/O & Peripheral Pin P48 (General)

PIN 1 VBAT

Power

Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))

Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32U575CIT6Q (LQFP-48(7x7)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32U575CIT6Q (LQFP-48(7x7)) - 2. Standard Pinout (Top View)

True package pinout (48 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32U575CIT6Q (LQFP-48(7x7)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32U575CIT6Q (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)

LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32U575CIT6Q (LQFP-48(7x7)) - 5. Recommended Land Pattern

IPC-7351B Footprint (48 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32U575CIT6Q (LQFP-48(7x7)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for STM32U575

P91 · p91_fig01EXACT PACKAGE

Figure 7. LQFP48_SMPS pinout

P91 · p91_fig02EXACT PACKAGE

P91 · p91_fig01P91

Datasheet Page 91 (p91_fig01)

P92 · p92_fig011546×981px

Figure 9. UFQFPN48_SMPS pinout

P92 · p92_fig021546×1328px

PA0

P146 · p146_fig011546×1780px

Figure 24. STM32U575xx power supply scheme (without SMPS)

P146 · p146_fig01P146

Datasheet Page 146 (p146_fig01)

P147 · p147_fig011546×1981px

Figure 25. STM32U575xQ power supply scheme (with SMPS)

P209 · p209_fig011545×701px

Figure 32. Typical application with a 8 MHz crystal

P240 · p240_fig011751×981px

Figure 38. ADC accuracy characteristics

P240 · p240_fig021546×738px

Figure 39. Typical connection diagram when using the ADC

P313 · p313_fig011875×1420px

Figure 92. WLCSP90 - Recommended footprint

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32U575CIT6Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32U575CIT6Q (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART interfaces.

Operating Supply VoltageV_CC / V_DD

1.71 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

160 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

12 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

7.00 × 7.00 × 1.60 mm (A1=0.10 mm)

Package family: LQFP (LQFP-48(7x7))

Pin Count & Lead PitchN / e

48 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol48 auto-grouped pins

IPC-7351B Land Pattern48 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

7.00 × 7.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.60mm · e=0.50mm

Pad Size (W × L)Level B

0.25 × 1.25 mm

Pins / Total PadsTopology

48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit LQFP-48(7x7)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32U575CIT6Q (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32U575CIT6Q (LQFP-48(7x7))?

Manufactured by ST, the STM32U575CIT6Q is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN -_ (PH0): Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)), 6 (PH1OSC OUT -_ (PH1): Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32U575CIT6Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U575CIT6Q (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U575CIT6Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U575CIT6Q (ST, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & STM32U575 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VBAT	Power_In	Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2	PC13	Digital_IO	Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
3	PC14 - OSC32_IN (PC14)	Digital_IO	Signal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
4	NC	No_Connect	No Connect (Leave Floating)
5	PH0OSC IN -_ (PH0)	Digital_IO	Signal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK.
6	PH1OSC OUT -_ (PH1)	Digital_IO	Signal terminal PH1OSC OUT -_ (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_ (PH1). Supported peripheral buses: RTC/CLK.
7	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
10	PA0	Digital_IO	Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RDYUSART2CTS. Supported peripheral buses: UART, SPI, ADC, PWM.
11	PA1	Digital_IO	Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK_USART2RTSDE. Supported peripheral buses: UART, SPI, ADC, PWM.
12	PA2	Digital_IO	Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
13	PA3	Digital_IO	Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
14	PA4	Digital_IO	Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
15	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, DAC, PWM.
16	PA6	Digital_IO	Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
17	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI1_MOSI. Supported peripheral buses: UART, SPI, I2C, ADC, PWM.
18	PB0	Digital_IO	Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSUSART3CK. Supported peripheral buses: SPI, ADC, PWM.
19	PB1	Digital_IO	Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
20	PB2	Digital_IO	Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: I2C, ADC, RTC/CLK.
21	P21	Digital_IO	Signal terminal P21 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P21. Supported peripheral buses: General.
22	P22	Digital_IO	Signal terminal P22 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P22. Supported peripheral buses: General.
23	P23	Digital_IO	Signal terminal P23 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P23. Supported peripheral buses: General.
24	P24	Digital_IO	Signal terminal P24 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P24. Supported peripheral buses: General.
25	P25	Digital_IO	Signal terminal P25 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P25. Supported peripheral buses: General.
26	P26	Digital_IO	Signal terminal P26 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P26. Supported peripheral buses: General.
27	P27	Digital_IO	Signal terminal P27 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P27. Supported peripheral buses: General.
28	P28	Digital_IO	Signal terminal P28 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P28. Supported peripheral buses: General.
29	P29	Digital_IO	Signal terminal P29 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P29. Supported peripheral buses: General.
30	P30	Digital_IO	Signal terminal P30 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P30. Supported peripheral buses: General.
31	P31	Digital_IO	Signal terminal P31 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P31. Supported peripheral buses: General.
32	P32	Digital_IO	Signal terminal P32 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P32. Supported peripheral buses: General.
33	P33	Digital_IO	Signal terminal P33 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P33. Supported peripheral buses: General.
34	P34	Digital_IO	Signal terminal P34 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P34. Supported peripheral buses: General.
35	P35	Digital_IO	Signal terminal P35 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P35. Supported peripheral buses: General.
36	P36	Digital_IO	Signal terminal P36 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P36. Supported peripheral buses: General.
37	P37	Digital_IO	Signal terminal P37 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P37. Supported peripheral buses: General.
38	P38	Digital_IO	Signal terminal P38 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P38. Supported peripheral buses: General.
39	P39	Digital_IO	Signal terminal P39 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P39. Supported peripheral buses: General.
40	P40	Digital_IO	Signal terminal P40 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P40. Supported peripheral buses: General.
41	P41	Digital_IO	Signal terminal P41 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P41. Supported peripheral buses: General.
42	P42	Digital_IO	Signal terminal P42 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P42. Supported peripheral buses: General.
43	P43	Digital_IO	Signal terminal P43 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P43. Supported peripheral buses: General.
44	P44	Digital_IO	Signal terminal P44 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P44. Supported peripheral buses: General.
45	P45	Digital_IO	Signal terminal P45 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P45. Supported peripheral buses: General.
46	P46	Digital_IO	Signal terminal P46 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P46. Supported peripheral buses: General.
47	P47	Digital_IO	Signal terminal P47 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P47. Supported peripheral buses: General.
48	P48	Digital_IO	Signal terminal P48 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: P48. Supported peripheral buses: General.

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