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STM32G484VEH6 (TFBGA-100(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32G484VEH6

STID: C5270378TFBGA-100(8x8) · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32G484VEH6 (TFBGA-100(8x8))A1PE4A2PB9A3PB8-BOOT0A4PB6A5PB3A6PD6A7PD5A8PD4A9PD1A10PC12B1PE5B2PE3B3PE1B4PB7B5PB5B6PD7B7PD2B8PD0B9PA15B10PA14C1PC14-OSC32_IC2PE6C3PE2C4PE0C5PB4C6PD3C7PC11C8PC10C9PA12C10PA11D1PC15-OSC32_OD2VSSD3VBATD4PC13D5VDDD6VSSD7VDDD8PA13D9PA10D10PA9E1PF0-OSC_INE2PF1-OSC_OUTE3PF9E4PF10E5VSSE6VSSE7VSSE8PC8E9PC9E10PA8K10PD8K9PB15K8PB12K7PE13K6PE10K5VREF+K4VSSAK3PB1K2PC4K1PA7J10PD12J9PB13J8PB10J7PE14J6PE11J5VDDAJ4PB2J3PC5J2PA6J1PA5H10PD11H9PB14H8PB11H7PE15H6PE9H5PE8H4PB0H3PA3H2PA4H1PA2G10PD15G9PD13G8PD9G7PD10G6PE12G5PE7G4PA0G3PF2G2PA1G1PC3F10PC7F9PC6F8PD14F7VDDF6VSSF5VDDF4PC1F3PG10-NRSTF2PC0F1PC2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=8.00mm · Pitch e=0.80mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
A2PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A3PB8-BOOT0I/OMultiplexed I/O & Peripheral Pin PB8-BOOT0 (General)
A4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
A7PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
A8PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
A9PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
A10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
B1PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
B2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B3PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
B4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
B5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
B6PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
B7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
B8PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
B9PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
B10PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
C1PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
C2PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
C3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
C4PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C5PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
C6PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
C7PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
C8PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
C9PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D1PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
D2VSSGNDGround Reference Pin (VSS)
D3VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D4PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
D5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D6VSSGNDGround Reference Pin (VSS)
D7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D8PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
D9PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
E1PF0-OSC_INI/OMultiplexed I/O & Peripheral Pin PF0-OSC_IN (RTC/CLK)
E2PF1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK)
E3PF9I/OMultiplexed I/O & Peripheral Pin PF9 (General)
E4PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
E5VSSGNDGround Reference Pin (VSS)
E6VSSGNDGround Reference Pin (VSS)
E7VSSGNDGround Reference Pin (VSS)
E8PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
E9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E10PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
F1PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
F2PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
F3PG10-NRSTI/OMultiplexed I/O & Peripheral Pin PG10-NRST (General)
F4PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
F5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F6VSSGNDGround Reference Pin (VSS)
F7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F8PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
F9PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
G1PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
G2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
G3PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
G4PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
G5PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
G6PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
G7PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
G8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
G9PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
G10PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
H1PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
H2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
H3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
H4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
H5PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
H6PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
H7PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
H8PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
H9PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
H10PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
J1PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
J2PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
J3PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
J4PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
J5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
J6PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
J7PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
J8PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
J9PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
J10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
K1PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
K2PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
K3PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
K4VSSAGNDGround Reference Pin (VSSA)
K5VREF+I/OMultiplexed I/O & Peripheral Pin VREF+ (General)
K6PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
K7PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
K8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
K9PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
K10PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
PIN A1 PE4
I/O
Multiplexed I/O & Peripheral Pin PE4 (General)
Design note: Signal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32G484VEH6 (ST · TFBGA-100(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32G484VEH6 (TFBGA-100(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32G484VEH6 (TFBGA-100(8x8)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32G484VEH6 (TFBGA-100(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32G484VEH6 (TFBGA-100(8x8)) - 4. Package Dimensions (D×E×A)
TFBGA-100(8x8) · 8.00×8.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32G484VEH6 (TFBGA-100(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32G484VEH6 (TFBGA-100(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (STM32G484VEH6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32G484VEH6 (TFBGA-100(8x8)) is a 100-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100(8x8))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-100(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32G484VEH6 (TFBGA-100(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32G484VEH6 (TFBGA-100(8x8))?

Manufactured by ST, the STM32G484VEH6 is housed in a TFBGA-100(8x8) package with 100 pins and a 0.80 mm lead pitch. Key pins include: A1 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), A2 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A3 (PB8-BOOT0: Multiplexed I/O & Peripheral Pin PB8-BOOT0 (General)), A4 (PB6: Multiplexed I/O & Peripheral Pin PB6 (General)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A6 (PD6: Multiplexed I/O & Peripheral Pin PD6 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32G484VEH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G484VEH6 (TFBGA-100(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G484VEH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G484VEH6 (ST, TFBGA-100(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32G483 / STM32G484 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
A2PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A3PB8-BOOT0Digital_IOSignal terminal PB8-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8-BOOT0. Supported peripheral buses: General.
A4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A7PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
A8PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
A9PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
A10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
B1PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
B2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B3PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
B4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
B5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
B6PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
B7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
B8PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
B9PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
B10PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
C1PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
C2PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
C3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
C4PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C5PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
C6PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
C7PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
C8PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
C9PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D1PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
D2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D3VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D4PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
D5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D8PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
D9PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
E1PF0-OSC_INDigital_IOSignal terminal PF0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0-OSC_IN. Supported peripheral buses: RTC/CLK.
E2PF1-OSC_OUTDigital_IOSignal terminal PF1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1-OSC_OUT. Supported peripheral buses: RTC/CLK.
E3PF9Digital_IOSignal terminal PF9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF9. Supported peripheral buses: General.
E4PF10Digital_IOSignal terminal PF10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General.
E5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E8PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
E9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E10PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
F1PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
F2PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
F3PG10-NRSTDigital_IOSignal terminal PG10-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10-NRST. Supported peripheral buses: General.
F4PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
F5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
F9PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
G1PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
G2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
G3PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
G4PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
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