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STM32G0B1VEI6 (UFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32G0B1VEI6

STID: C5270226UFBGA-100 · 100 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32G0B1VEI6 (UFBGA-100)A1PB8A2PE3A3PE2A4PE0A5PB3A6PF13A7PF11A8PF9A9PD6A10PD5A11PD2A12PC9B1PC11B2PC10B3PB7B4PE1B5PB4B6PF12B7PF10B8PD7B9PD4B10PD0B11PA15B12PA14-BOOT0C1PE6C2PE4C3PB9C4PB6C5PB5C8PD3C9PD1C10PC8C11PA13C12PA12[PA10]D1PC14-OSC32_ID2PC12D3PE5D10PF8D11PD15D12PA11[PA9]E1PC15-OSC32_OE2VBATE3PC13E10PA10E11PD14E12PD13F1VDDF2VREF+F11PD12F12VDDIO2M12PB13M11PB10M10PE13M9PE11M8PE8M7PE7M6PF6M5PB1M4PC5M3PA6M2PA5M1PA2L12PA8L11PB11L10PE15L9PE12L8PE10L7PF7L6PB2L5PB0L4PC4L3PA4L2PA1L1PC3K12PC7K11PB14K10PB12K9PE14K8PE9K5PA7K4PA3K3PA0K2PC2K1PC0J12PD8J11PC6J10PB15J3PC1J2PF5J1PF1-OSC_OUTH12PD10H11PD9H10PA9H3PF3H2PF4H1PF0-OSC_ING12VSSG11PD11G2PF2-NRSTG1VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1M1A2B2C2D2E2F2G2H2J2K2L2M2A3B3C3D3E3H3J3K3L3M3A4B4C4K4L4M4A5B5C5K5L5M5A6B6L6M6A7B7L7M7A8B8C8K8L8M8A9B9C9K9L9M9A10B10C10D10E10H10J10K10L10M10A11B11C11D11E11F11G11H11J11K11L11M11A12B12C12D12E12F12G12H12J12K12L12M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
A2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
A4PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A6PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
A7PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
A8PF9I/OMultiplexed I/O & Peripheral Pin PF9 (General)
A9PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
A10PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
A11PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A12PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
B1PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B2PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
B4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
B5PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B6PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
B7PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
B8PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
B9PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
B10PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
B11PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
B12PA14-BOOT0I/OMultiplexed I/O & Peripheral Pin PA14-BOOT0 (General)
C1PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
C2PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
C3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
C4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
C8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
C9PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
C10PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
C11PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
C12PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (General)
D1PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
D2PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
D3PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
D10PF8I/OMultiplexed I/O & Peripheral Pin PF8 (General)
D11PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
D12PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (General)
E1PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
E2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
E3PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
E10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
E11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
E12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
F1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F2VREF+I/OMultiplexed I/O & Peripheral Pin VREF+ (General)
F11PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
F12VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
G1VSSGNDGround Reference Pin (VSS)
G2PF2-NRSTI/OMultiplexed I/O & Peripheral Pin PF2-NRST (General)
G11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
G12VSSGNDGround Reference Pin (VSS)
H1PF0-OSC_INI/OMultiplexed I/O & Peripheral Pin PF0-OSC_IN (RTC/CLK)
H2PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
H3PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
H10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
H11PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
H12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
J1PF1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK)
J2PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
J3PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
J10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
J11PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
J12PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
K1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
K2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
K3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
K4PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
K5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
K8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
K9PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
K10PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
K12PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
L1PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
L2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
L3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
L4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
L5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
L6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
L7PF7I/OMultiplexed I/O & Peripheral Pin PF7 (General)
L8PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
L9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
L10PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
L11PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
L12PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
M1PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
M2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
M3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
M4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
M5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
M6PF6I/OMultiplexed I/O & Peripheral Pin PF6 (General)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M8PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
M9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
M10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
M11PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
M12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
PIN A1 PB8
I/O
Multiplexed I/O & Peripheral Pin PB8 (General)
Design note: Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32G0B1VEI6 (ST · UFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32G0B1VEI6 (UFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32G0B1VEI6 (UFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32G0B1VEI6 (UFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32G0B1VEI6 (UFBGA-100) - 4. Package Dimensions (D×E×A)
UFBGA-100 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32G0B1VEI6 (UFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32G0B1VEI6 (UFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (STM32G0B1VEI6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32G0B1VEI6 (UFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.58 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.58 mm (A1=0.20 mm)
Package family: BGA (UFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.58mm · e=0.50mm
Pad Size (W × L)Level B
0.23 × 0.23 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32G0B1VEI6 (UFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32G0B1VEI6 (UFBGA-100)?

Manufactured by ST, the STM32G0B1VEI6 is housed in a UFBGA-100 package with 100 pins and a 0.50 mm lead pitch. Key pins include: A1 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), A2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A6 (PF13: Multiplexed I/O & Peripheral Pin PF13 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32G0B1VEI6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G0B1VEI6 (UFBGA-100) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G0B1VEI6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G0B1VEI6 (ST, UFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32G0B1VEI Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
A2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
A4PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A6PF13Digital_IOSignal terminal PF13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General.
A7PF11Digital_IOSignal terminal PF11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF11. Supported peripheral buses: General.
A8PF9Digital_IOSignal terminal PF9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF9. Supported peripheral buses: General.
A9PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A10PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
A11PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A12PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
B1PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B2PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
B4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
B5PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B6PF12Digital_IOSignal terminal PF12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General.
B7PF10Digital_IOSignal terminal PF10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General.
B8PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
B9PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
B10PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
B11PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
B12PA14-BOOT0Digital_IOSignal terminal PA14-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14-BOOT0. Supported peripheral buses: General.
C1PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
C2PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
C3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
C4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
C8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
C9PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
C10PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
C11PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
C12PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12[PA10]. Supported peripheral buses: General.
D1PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
D2PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
D3PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
D10PF8Digital_IOSignal terminal PF8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF8. Supported peripheral buses: General.
D11PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
D12PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11[PA9]. Supported peripheral buses: General.
E1PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
E2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E3PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
E10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
E11PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
E12PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
F1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F2VREF+Digital_IOSignal terminal VREF+ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
F11PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
F12VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G2PF2-NRSTDigital_IOSignal terminal PF2-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: General.
G11PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
G12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
H1PF0-OSC_INDigital_IOSignal terminal PF0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0-OSC_IN. Supported peripheral buses: RTC/CLK.
H2PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
H3PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
H10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
H11PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
H12PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
J1PF1-OSC_OUTDigital_IOSignal terminal PF1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1-OSC_OUT. Supported peripheral buses: RTC/CLK.
J2PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
J3PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
J10PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
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