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CH32H417WEU6 (QFN-68(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32H417WEU6

WCHID: C52196060QFN-68(8x8) · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32H417WEU6 (QFN-68(8x8))1V DD332PE33PE44PE55PE66V DDK7MDIRN8MDIRP9MDITN10MDITP11V DD3312VDD3313XI14XO15PC0/ADC10/HS16PC1/ADC11/HS17PC2/ADC12/HS18PC3/ADC13/HS19VDD33A20PA5/ADC5/OP121PB0/ADC8/OP122PB1/ADC9/OP123PE1324PE1425PE1526PB1027PB1128VIO1829VDDIO30PB1231PB1332PB1433PD1034PD1135PD1269VSS68PB9/USB2DM/S67PB8/USB2DP/S66VIO1865PF1464PE163PE062PF561PF460PF359PD758PD657PD556PD455PD354PD253PD152PD051PC1250PC1149PC1048PA1547PA1446PA1345PC944PC843PC742PC641PF240PF139PF038PD1537PD1436PD13Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.850.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1V DD33I/OMultiplexed I/O & Peripheral Pin V DD33 (General)
2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
4PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
5PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
6V DDKI/OMultiplexed I/O & Peripheral Pin V DDK (General)
7MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
8MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
9MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
10MDITPI/OMultiplexed I/O & Peripheral Pin MDITP (General)
11V DD33I/OMultiplexed I/O & Peripheral Pin V DD33 (General)
12VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
13XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
14XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
15PC0/ADC10/HSADC0I/OMultiplexed I/O & Peripheral Pin PC0/ADC10/HSADC0 (ADC)
16PC1/ADC11/HSADC1I/OMultiplexed I/O & Peripheral Pin PC1/ADC11/HSADC1 (ADC)
17PC2/ADC12/HSADC2I/OMultiplexed I/O & Peripheral Pin PC2/ADC12/HSADC2 (ADC)
18PC3/ADC13/HSADC3I/OMultiplexed I/O & Peripheral Pin PC3/ADC13/HSADC3 (ADC)
19VDD33APowerPower Supply Input (VDD33A — 3.3V / 5.0V Standard Logic)
20PA5/ADC5/OP1_O1/DAC2I/OMultiplexed I/O & Peripheral Pin PA5/ADC5/OP1_O1/DAC2 (ADC, DAC)
21PB0/ADC8/OP1_P0/CMP_P0I/OMultiplexed I/O & Peripheral Pin PB0/ADC8/OP1_P0/CMP_P0 (ADC)
22PB1/ADC9/OP1_N0/CMP_N0I/OMultiplexed I/O & Peripheral Pin PB1/ADC9/OP1_N0/CMP_N0 (ADC)
23PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
24PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
25PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
26PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
27PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
28VIO18I/OMultiplexed I/O & Peripheral Pin VIO18 (General)
29VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
30PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
31PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
32PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
33PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
34PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
35PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
36PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
37PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
38PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
39PF0I/OMultiplexed I/O & Peripheral Pin PF0 (General)
40PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
41PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
42PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
43PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
44PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
45PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
46PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
47PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
48PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
49PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
50PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
51PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
52PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
53PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
54PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
55PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
56PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
57PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
58PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
59PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
60PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
61PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
62PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
63PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
64PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
65PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
66VIO18I/OMultiplexed I/O & Peripheral Pin VIO18 (General)
67PB8/USB2DP/SWCLKI/OMultiplexed I/O & Peripheral Pin PB8/USB2DP/SWCLK (USB, SWD/JTAG)
68PB9/USB2DM/SWDIOI/OMultiplexed I/O & Peripheral Pin PB9/USB2DM/SWDIO (USB, SWD/JTAG)
69VSSGNDGround Reference Pin (VSS)
PIN 1 V DD33
I/O
Multiplexed I/O & Peripheral Pin V DD33 (General)
Design note: V - DD33
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32H417WEU6 (WCH · QFN-68(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32H417WEU6 (QFN-68(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32H417WEU6 (QFN-68(8x8)) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32H417WEU6 (QFN-68(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32H417WEU6 (QFN-68(8x8)) - 4. Package Dimensions (D×E×A)
QFN-68(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32H417WEU6 (QFN-68(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32H417WEU6 (QFN-68(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH32H417
P127 · p127_fig01EXACT PACKAGE
CH32H417WEU6 (QFN-68(8x8)) — CH32H417、H416、H415 数据手册 https://wch.cn
CH32H417、H416、H415 数据手册 https://wch.cn
P24 · p24_fig011643×1622px
CH32H417WEU6 (QFN-68(8x8)) — 2.1 引脚排列 2.1.1 CH32H417 引脚排列 | 49 | 42 | 40 39 | 41 | 37 | 54 | 38 | 45 | 48 | 34 | 47 | 43 | 46 | 50 51 52 | 44 | 53 | 36 | 33 | 35 | 58 57 56 55 | 59 60 61 62 63 64 | 65 | 71 | 68 69 | 79 | 70 | 83 | 72 73 74 75 76 77 78 | 67 66 | 80 81 |
2.1 引脚排列 2.1.1 CH32H417 引脚排列 | 49 | 42 | 40 39 | 41 | 37 | 54 | 38 | 45 | 48 | 34 | 47 | 43 | 46 | 50 51 52 | 44 | 53 | 36 | 33 | 35 | 58 57 56 55 | 59 60 61 62 63 64 | 65 | 71 | 68 69 | 79 | 70 | 83 | 72 73 74 75 76 77 78 | 67 66 | 80 81 |
P24 · p24_fig01P24
CH32H417WEU6 (QFN-68(8x8)) — Datasheet Page 24 (p24_fig01)
Datasheet Page 24 (p24_fig01)
P26 · p26_fig011114×1115px
CH32H417WEU6 (QFN-68(8x8)) — 31
31
P26 · p26_fig021069×1070px
CH32H417WEU6 (QFN-68(8x8)) — 示例：ADC_:(ADC0:ADC_IN0)
示例：ADC_:(ADC0:ADC_IN0)

Technical Specifications & Part Details (CH32H417WEU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32H417WEU6 (QFN-68(8x8)) is a 68-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, SDIO, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
150MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-68(8x8))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, SDIO, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 5.80×5.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-68(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-68(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32H417WEU6 (QFN-68(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32H417WEU6 (QFN-68(8x8))?

Manufactured by WCH, the CH32H417WEU6 is housed in a QFN-68(8x8) package with 69 pins and a 0.40 mm lead pitch. Key pins include: 1 (V DD33: Multiplexed I/O & Peripheral Pin V DD33 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), 6 (V DDK: Multiplexed I/O & Peripheral Pin V DDK (General)).

What are the IPC-7351B PCB Footprint dimensions for CH32H417WEU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32H417WEU6 (QFN-68(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 5.80 × 5.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32H417WEU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32H417WEU6 (WCH, QFN-68(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & CH32H417 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1V DD33Digital_IOSignal terminal V DD33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V DD33. Supported peripheral buses: General.
2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
4PE5Digital_IOSignal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
5PE6Digital_IOSignal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
6V DDKDigital_IOSignal terminal V DDK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V DDK. Supported peripheral buses: General.
7MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
8MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
9MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
10MDITPDigital_IOSignal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
11V DD33Digital_IOSignal terminal V DD33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V DD33. Supported peripheral buses: General.
12VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
14XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
15PC0/ADC10/HSADC0AnalogSignal terminal PC0/ADC10/HSADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0/ADC10/HSADC0. Supported peripheral buses: ADC.
16PC1/ADC11/HSADC1AnalogSignal terminal PC1/ADC11/HSADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1/ADC11/HSADC1. Supported peripheral buses: ADC.
17PC2/ADC12/HSADC2AnalogSignal terminal PC2/ADC12/HSADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2/ADC12/HSADC2. Supported peripheral buses: ADC.
18PC3/ADC13/HSADC3AnalogSignal terminal PC3/ADC13/HSADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3/ADC13/HSADC3. Supported peripheral buses: ADC.
19VDD33APower_InPrimary positive power supply input (VDD33A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20PA5/ADC5/OP1_O1/DAC2AnalogSignal terminal PA5/ADC5/OP1_O1/DAC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5/OP1_O1/DAC2. Supported peripheral buses: ADC, DAC.
21PB0/ADC8/OP1_P0/CMP_P0AnalogSignal terminal PB0/ADC8/OP1_P0/CMP_P0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8/OP1_P0/CMP_P0. Supported peripheral buses: ADC.
22PB1/ADC9/OP1_N0/CMP_N0AnalogSignal terminal PB1/ADC9/OP1_N0/CMP_N0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9/OP1_N0/CMP_N0. Supported peripheral buses: ADC.
23PE13Digital_IOSignal terminal PE13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE13. Supported peripheral buses: General.
24PE14Digital_IOSignal terminal PE14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General.
25PE15Digital_IOSignal terminal PE15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE15. Supported peripheral buses: General.
26PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
27PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
28VIO18Digital_IOSignal terminal VIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO18. Supported peripheral buses: General.
29VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
31PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
32PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
33PD10Digital_IOSignal terminal PD10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
34PD11Digital_IOSignal terminal PD11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
35PD12Digital_IOSignal terminal PD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
36PD13Digital_IOSignal terminal PD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
37PD14Digital_IOSignal terminal PD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
38PD15Digital_IOSignal terminal PD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
39PF0Digital_IOSignal terminal PF0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
40PF1Digital_IOSignal terminal PF1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
41PF2Digital_IOSignal terminal PF2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
42PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
43PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
44PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
45PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
46PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
47PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
48PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
49PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
50PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
51PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
52PD0Digital_IOSignal terminal PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
53PD1Digital_IOSignal terminal PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
54PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
55PD3Digital_IOSignal terminal PD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
56PD4Digital_IOSignal terminal PD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
57PD5Digital_IOSignal terminal PD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
58PD6Digital_IOSignal terminal PD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
59PD7Digital_IOSignal terminal PD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
60PF3Digital_IOSignal terminal PF3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
61PF4Digital_IOSignal terminal PF4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
62PF5Digital_IOSignal terminal PF5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
63PE0Digital_IOSignal terminal PE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
64PE1Digital_IOSignal terminal PE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
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