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CH9434D (QFN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9434D

WCHID: C51912925QFN-20(3x3) · 21 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9434D (QFN-20(3x3))1PIN12 PIN13 2PIN5 PIN6 、3PIN9 PIN10 、4PIN7 PIN8 、5PIN2 PIN3 、6PIN14 PIN15 7-8RXD49CTS310RXD311SCS/AD021GND20MISO/AD119MOSI/SDA18SCK/SCL17RTS4/INT#/SE16/TNOW315/TNOW114/TNOW013IO1512/TNOW1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.40mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PIN12 PIN13 、I/OMultiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)
2PIN5 PIN6 、I/OMultiplexed I/O & Peripheral Pin PIN5 PIN6 、 (UART)
3PIN9 PIN10 、I/OMultiplexed I/O & Peripheral Pin PIN9 PIN10 、 (UART)
4PIN7 PIN8 、I/OMultiplexed I/O & Peripheral Pin PIN7 PIN8 、 (UART)
5PIN2 PIN3 、I/OMultiplexed I/O & Peripheral Pin PIN2 PIN3 、 (RTC/CLK)
6PIN14 PIN15 、I/OMultiplexed I/O & Peripheral Pin PIN14 PIN15 、 (CAN)
7-I/OMultiplexed I/O & Peripheral Pin - (General)
8RXD4I/OMultiplexed I/O & Peripheral Pin RXD4 (UART)
9CTS3I/OMultiplexed I/O & Peripheral Pin CTS3 (UART)
10RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
11SCS/AD0I/OMultiplexed I/O & Peripheral Pin SCS/AD0 (General)
12/TNOW1I/OMultiplexed I/O & Peripheral Pin /TNOW1 (UART)
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14/TNOW0I/OMultiplexed I/O & Peripheral Pin /TNOW0 (UART)
15/TNOW1I/OMultiplexed I/O & Peripheral Pin /TNOW1 (UART)
16/TNOW3I/OMultiplexed I/O & Peripheral Pin /TNOW3 (UART)
17RTS4/INT#/SELI/OMultiplexed I/O & Peripheral Pin RTS4/INT#/SEL (UART)
18SCK/SCLI/OMultiplexed I/O & Peripheral Pin SCK/SCL (SPI, I2C)
19MOSI/SDAI/OMultiplexed I/O & Peripheral Pin MOSI/SDA (SPI, I2C)
20MISO/AD1I/OMultiplexed I/O & Peripheral Pin MISO/AD1 (SPI)
21GNDGNDGround Reference Pin (GND)
PIN 1 PIN12 PIN13 、
I/O
Multiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)
Design note: UART0_TXRX_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9434D (WCH · QFN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9434D (QFN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9434D (QFN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9434D (QFN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9434D (QFN-20(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9434D (QFN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9434D (QFN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for CH9434
P1 · p01_fig011493×518px
CH9434D (QFN-20(3x3)) — CH9434D 是一款SPI/IIC 转四串口和一路CAN 扩展芯片，提供四组全双工异步串口，用于单片机 /嵌入式系统扩展异步串口。CH9434D 包含四个兼容16C550 的异步串口，最高支持6Mbps 波特率通讯。 最多支持4 路GPIO，提供半双工收发自动切换引脚TNOW，提供一路CAN 收发控制器。
CH9434D 是一款SPI/IIC 转四串口和一路CAN 扩展芯片，提供四组全双工异步串口，用于单片机 /嵌入式系统扩展异步串口。CH9434D 包含四个兼容16C550 的异步串口，最高支持6Mbps 波特率通讯。 最多支持4 路GPIO，提供半双工收发自动切换引脚TNOW，提供一路CAN 收发控制器。
P1 · p01_fig021494×619px
CH9434D (QFN-20(3x3)) — 2、特点
2、特点
P1 · p01_fig02P1
CH9434D (QFN-20(3x3)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P3 · p03_fig011318×1269px
CH9434D (QFN-20(3x3)) — SCS/AD0 11 TXD0 12 RXD0 13 CTS0/TNOW0/GPIO 0/CAN_RX 14 RTS0/TNOW1/GPIO 1/CAN_TX 15
SCS/AD0 11 TXD0 12 RXD0 13 CTS0/TNOW0/GPIO 0/CAN_RX 14 RTS0/TNOW1/GPIO 1/CAN_TX 15
P3 · p03_fig021045×1002px
CH9434D (QFN-20(3x3)) — V1.6 3
V1.6 3
P3 · p03_fig01P3
CH9434D (QFN-20(3x3)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P40 · p40_fig01880×492px
CH9434D (QFN-20(3x3)) — 11.2 初始化串口 例1：CH9434A 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、读出串口1 的LCR 寄存器值，假设读出0x00。
11.2 初始化串口 例1：CH9434A 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、读出串口1 的LCR 寄存器值，假设读出0x00。
P40 · p40_fig02883×492px
CH9434D (QFN-20(3x3)) — 2)、写串口1 的LCR 寄存器值，设DLAB 位，设8Bit 数据位，1Bit 停止位，无校验。
2)、写串口1 的LCR 寄存器值，设DLAB 位，设8Bit 数据位，1Bit 停止位，无校验。
P40 · p40_fig03883×491px
CH9434D (QFN-20(3x3)) — 3)、设置串口1 的波特率除数锁存器DLL 和DLM：32000000*15/13/8/115200 ≈ 40，DLL 为0x28， DLM 为0x00。
3)、设置串口1 的波特率除数锁存器DLL 和DLM：32000000*15/13/8/115200 ≈ 40，DLL 为0x28， DLM 为0x00。
P40 · p40_fig04883×492px
CH9434D (QFN-20(3x3)) — V1.6 40
V1.6 40
P41 · p41_fig011238×782px
CH9434D (QFN-20(3x3)) — SCS#
SCS#
P41 · p41_fig021238×805px
CH9434D (QFN-20(3x3)) — 例2：CH9434D 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、开启串口1 的引脚功能
例2：CH9434D 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、开启串口1 的引脚功能
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (CH9434D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9434D (QFN-20(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, SPI, I2C, CAN, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, SPI, I2C, CAN, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.90×1.90mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9434D (QFN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9434D (QFN-20(3x3))?

Manufactured by WCH, the CH9434D is housed in a QFN-20(3x3) package with 21 pins and a 0.40 mm lead pitch. Key pins include: 1 (PIN12 PIN13 、: Multiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)), 2 (PIN5 PIN6 、: Multiplexed I/O & Peripheral Pin PIN5 PIN6 、 (UART)), 3 (PIN9 PIN10 、: Multiplexed I/O & Peripheral Pin PIN9 PIN10 、 (UART)), 4 (PIN7 PIN8 、: Multiplexed I/O & Peripheral Pin PIN7 PIN8 、 (UART)), 5 (PIN2 PIN3 、: Multiplexed I/O & Peripheral Pin PIN2 PIN3 、 (RTC/CLK)), 6 (PIN14 PIN15 、: Multiplexed I/O & Peripheral Pin PIN14 PIN15 、 (CAN)).

What are the IPC-7351B PCB Footprint dimensions for CH9434D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9434D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.90 × 1.90 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9434D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9434D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH9434 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PIN12 PIN13 、Digital_IOSignal terminal PIN12 PIN13 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN12 PIN13 、. Supported peripheral buses: UART.
2PIN5 PIN6 、Digital_IOSignal terminal PIN5 PIN6 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN5 PIN6 、. Supported peripheral buses: UART.
3PIN9 PIN10 、Digital_IOSignal terminal PIN9 PIN10 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN9 PIN10 、. Supported peripheral buses: UART.
4PIN7 PIN8 、Digital_IOSignal terminal PIN7 PIN8 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN7 PIN8 、. Supported peripheral buses: UART.
5PIN2 PIN3 、Digital_IOSignal terminal PIN2 PIN3 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN2 PIN3 、. Supported peripheral buses: RTC/CLK.
6PIN14 PIN15 、Digital_IOSignal terminal PIN14 PIN15 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN14 PIN15 、. Supported peripheral buses: CAN.
7-Digital_IOSignal terminal - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: -. Supported peripheral buses: General.
8RXD4Digital_IOSignal terminal RXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD4. Supported peripheral buses: UART.
9CTS3Digital_IOSignal terminal CTS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS3. Supported peripheral buses: UART.
10RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
11SCS/AD0Digital_IOSignal terminal SCS/AD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS/AD0. Supported peripheral buses: General.
12/TNOW1Digital_IOSignal terminal /TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW1. Supported peripheral buses: UART.
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14/TNOW0Digital_IOSignal terminal /TNOW0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW0. Supported peripheral buses: UART.
15/TNOW1Digital_IOSignal terminal /TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW1. Supported peripheral buses: UART.
16/TNOW3Digital_IOSignal terminal /TNOW3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW3. Supported peripheral buses: UART.
17RTS4/INT#/SELDigital_IOSignal terminal RTS4/INT#/SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS4/INT#/SEL. Supported peripheral buses: UART.
18SCK/SCLDigital_IOSignal terminal SCK/SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK/SCL. Supported peripheral buses: SPI, I2C.
19MOSI/SDADigital_IOSignal terminal MOSI/SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MOSI/SDA. Supported peripheral buses: SPI, I2C.
20MISO/AD1Digital_IOSignal terminal MISO/AD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MISO/AD1. Supported peripheral buses: SPI.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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