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CH9101U (SSOP-28-209mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9101U

WCHID: C5187521SSOP-28-209mil · 28 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9101U (SSOP-28-209mil)1TXD2DTR3RTS4VIO5RXD6RI7GND8NC9DSR10DCD11CTS12SUSPEND/GPIO13TNOW/GPIO214ACT#/GPIO328NC27NC26NC25GND24GPIO623TXS/GPIO022RXS/GPIO121GND20VDD519RESET#18GND17V316UD-15UD+Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=5.30mm · Pitch e=0.65mmD=10.20mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 5.30mm × 10.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
2DTRI/OMultiplexed I/O & Peripheral Pin DTR (UART)
3RTSI/OMultiplexed I/O & Peripheral Pin RTS (UART)
4VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
5RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
6RII/OMultiplexed I/O & Peripheral Pin RI (General)
7GNDGNDGround Reference Pin (GND)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9DSRI/OMultiplexed I/O & Peripheral Pin DSR (UART)
10DCDI/OMultiplexed I/O & Peripheral Pin DCD (General)
11CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
12SUSPEND/GPIO4I/OMultiplexed I/O & Peripheral Pin SUSPEND/GPIO4 (General)
13TNOW/GPIO2I/OMultiplexed I/O & Peripheral Pin TNOW/GPIO2 (General)
14ACT#/GPIO3I/OMultiplexed I/O & Peripheral Pin ACT#/GPIO3 (General)
15UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
16UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
17V3PowerRegulated Power Output (V3 — 3.3V / 5.0V Standard Logic)
18GNDGNDGround Reference Pin (GND)
19RESET#ISystem Enable & Hardware Reset (RESET#)
20VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
21GNDGNDGround Reference Pin (GND)
22RXS/GPIO1I/OMultiplexed I/O & Peripheral Pin RXS/GPIO1 (General)
23TXS/GPIO0I/OMultiplexed I/O & Peripheral Pin TXS/GPIO0 (General)
24GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (General)
25GNDGNDGround Reference Pin (GND)
26NCI/OMultiplexed I/O & Peripheral Pin NC (General)
27NCI/OMultiplexed I/O & Peripheral Pin NC (General)
28NCI/OMultiplexed I/O & Peripheral Pin NC (General)
PIN 1 TXD
I/O
Multiplexed I/O & Peripheral Pin TXD (UART)
Design note: Signal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9101U (WCH · SSOP-28-209mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9101U (SSOP-28-209mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9101U (SSOP-28-209mil) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9101U (SSOP-28-209mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9101U (SSOP-28-209mil) - 4. Package Dimensions (D×E×A)
SSOP-28-209mil · 5.30×10.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9101U (SSOP-28-209mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9101U (SSOP-28-209mil) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (CH9101U)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9101U (SSOP-28-209mil) is a 28-pin standard electronic & interconnect component featuring a 10.20 × 5.30 × 2.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.20 × 5.30 × 2.00 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-28-209mil)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-28-209mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=2.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-28-209mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9101U (SSOP-28-209mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9101U (SSOP-28-209mil)?

Manufactured by WCH, the CH9101U is housed in a SSOP-28-209mil package with 28 pins and a 0.65 mm lead pitch. Key pins include: 1 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 2 (DTR: Multiplexed I/O & Peripheral Pin DTR (UART)), 3 (RTS: Multiplexed I/O & Peripheral Pin RTS (UART)), 4 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 5 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 6 (RI: Multiplexed I/O & Peripheral Pin RI (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9101U?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9101U (SSOP-28-209mil) has a nominal body envelope of 5.30 × 10.20 mm, pitch e = 0.65 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9101U?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9101U (WCH, SSOP-28-209mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & CH9101 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
2DTRDigital_IOSignal terminal DTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR. Supported peripheral buses: UART.
3RTSDigital_IOSignal terminal RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART.
4VIODigital_IOSignal terminal VIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
5RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
6RIDigital_IOSignal terminal RI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI. Supported peripheral buses: General.
7GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
8NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9DSRDigital_IOSignal terminal DSR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR. Supported peripheral buses: UART.
10DCDDigital_IOSignal terminal DCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD. Supported peripheral buses: General.
11CTSDigital_IOSignal terminal CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
12SUSPEND/GPIO4Digital_IOSignal terminal SUSPEND/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSPEND/GPIO4. Supported peripheral buses: General.
13TNOW/GPIO2Digital_IOSignal terminal TNOW/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW/GPIO2. Supported peripheral buses: General.
14ACT#/GPIO3Digital_IOSignal terminal ACT#/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT#/GPIO3. Supported peripheral buses: General.
15UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
16UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
17V3Power_OutRegulated power output rail (V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
20VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
22RXS/GPIO1Digital_IOSignal terminal RXS/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXS/GPIO1. Supported peripheral buses: General.
23TXS/GPIO0Digital_IOSignal terminal TXS/GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXS/GPIO0. Supported peripheral buses: General.
24GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General.
25GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
26NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
28NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
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