ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH9101R (QSOP-16-150mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9101R

WCHID: C5187520QSOP-16-150mil · 16 Pins · Pitch 0.64mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9101R (QSOP-16-150mil)1TXD2RTS3VIO4RXD5GND6CTS7TXS/DSR8UD+16SUSPEND/DTR15TNOW/DCD14RXS/RI13GND12VDD511RESET#10V39UD-Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.215.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=3.90mm · Pitch e=0.64mmD=4.90mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.90mm × 4.90mm · Pitch: 0.64mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
2RTSI/OMultiplexed I/O & Peripheral Pin RTS (UART)
3VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
4RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
5GNDGNDGround Reference Pin (GND)
6CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
7TXS/DSRI/OMultiplexed I/O & Peripheral Pin TXS/DSR (UART)
8UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
9UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
10V3PowerRegulated Power Output (V3 — 3.3V to 5V)
11RESET#ISystem Enable & Hardware Reset (RESET#)
12VDD5PowerPower Supply Input (VDD5 — 3.3V to 5V)
13GNDGNDGround Reference Pin (GND)
14RXS/RII/OMultiplexed I/O & Peripheral Pin RXS/RI (General)
15TNOW/DCDI/OMultiplexed I/O & Peripheral Pin TNOW/DCD (General)
16SUSPEND/DTRI/OMultiplexed I/O & Peripheral Pin SUSPEND/DTR (UART)
PIN 1 TXD
I/O
Multiplexed I/O & Peripheral Pin TXD (UART)
Design note: Signal terminal TXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9101R (WCH · QSOP-16-150mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9101R (QSOP-16-150mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9101R (QSOP-16-150mil) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9101R (QSOP-16-150mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9101R (QSOP-16-150mil) - 4. Package Dimensions (D×E×A)
QSOP-16-150mil · 3.90×4.90mm · Pitch 0.64mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9101R (QSOP-16-150mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9101R (QSOP-16-150mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH9101
P1 · p01_fig011463×442px
CH9101R (QSOP-16-150mil) — 图1-1 系统框图 2、特点
图1-1 系统框图 2、特点
P2 · p02_fig011654×1399px
CH9101R (QSOP-16-150mil) — 3、引脚排列
3、引脚排列
P2 · p02_fig021736×555px
CH9101R (QSOP-16-150mil) — CH9101 的USB 收发器按USB2.0 全内置设计，UD+和UD-引脚不能串接电阻，否则影响信号质量。 CH9101N 无内置EEPROM。
CH9101 的USB 收发器按USB2.0 全内置设计，UD+和UD-引脚不能串接电阻，否则影响信号质量。 CH9101N 无内置EEPROM。
P2 · p02_fig01P2
CH9101R (QSOP-16-150mil) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P10 · p10_fig011279×1085px
CH9101R (QSOP-16-150mil) — 7.5 SOP8
7.5 SOP8
P10 · p10_fig021452×974px
CH9101R (QSOP-16-150mil) — 图8-1 USB 转9 线TTL 串口的参考电路图
图8-1 USB 转9 线TTL 串口的参考电路图
P10 · p10_fig02P10
CH9101R (QSOP-16-150mil) — Datasheet Page 10 (p10_fig02)
Datasheet Page 10 (p10_fig02)
P11 · p11_fig01899×663px
CH9101R (QSOP-16-150mil) — 图8-2 USB 转9 线RS232 串口的参考电路图
图8-2 USB 转9 线RS232 串口的参考电路图
P11 · p11_fig02849×382px
CH9101R (QSOP-16-150mil) — 图8-3 USB 转RS485 的参考电路图
图8-3 USB 转RS485 的参考电路图

Technical Specifications & Part Details (CH9101R)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9101R (QSOP-16-150mil) is a 16-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.10 mm mechanical envelope (lead pitch e = 0.64 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.10 mm (A1=0.15 mm)
Package family: TSSOP (QSOP-16-150mil)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.64 mm (25.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 0.64mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QSOP-16-150mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=0.64mm
Pad Size (W × L)Level B
0.38 × 1.50 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QSOP-16-150mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9101R (QSOP-16-150mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9101R (QSOP-16-150mil)?

Manufactured by WCH, the CH9101R is housed in a QSOP-16-150mil package with 16 pins and a 0.64 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 2 (RTS: Multiplexed I/O & Peripheral Pin RTS (UART)), 3 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 4 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 5 (GND: Ground Reference Pin (GND)), 6 (CTS: Multiplexed I/O & Peripheral Pin CTS (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH9101R?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9101R (QSOP-16-150mil) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 0.64 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9101R?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9101R (WCH, QSOP-16-150mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & CH9101 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1TXDDigital_IOSignal terminal TXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
2RTSDigital_IOSignal terminal RTS (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART.
3VIODigital_IOSignal terminal VIO (I/O, 3.3V to 5V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
4RXDDigital_IOSignal terminal RXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6CTSDigital_IOSignal terminal CTS (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
7TXS/DSRDigital_IOSignal terminal TXS/DSR (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXS/DSR. Supported peripheral buses: UART.
8UD+Digital_IOSignal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
9UD-Digital_IOSignal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
10V3Power_OutRegulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V).
11RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
12VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V to 5V domain (Max rating: 5.0V).
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14RXS/RIDigital_IOSignal terminal RXS/RI (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXS/RI. Supported peripheral buses: General.
15TNOW/DCDDigital_IOSignal terminal TNOW/DCD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TNOW/DCD. Supported peripheral buses: General.
16SUSPEND/DTRDigital_IOSignal terminal SUSPEND/DTR (I/O, 3.3V to 5V domain). Multiplexed alternate functions: SUSPEND/DTR. Supported peripheral buses: UART.
ExplorePartsPackagesMFRsUpload