ChipDocs.org
⌘K
2284 PARTSUpload PDF
C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) — Symbol, Footprint IPC-7351B & 3D STEP Model

C5187519

SemiconductorQFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1 · 17 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1)1VIO2RXD3GND4CTS5TXS/DSR6UD+7UD-8V39RESET#17GND16RTS15TXD14SUSPEND/DTR13GND12TNOW/DCD11RXS/RI10VDD5Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1712111094321876513141516E=4.00mm · Pitch e=0.65mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (17/17)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
2RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
3GNDGNDGround Reference Pin (GND)
4CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
5TXS/DSRI/OMultiplexed I/O & Peripheral Pin TXS/DSR (UART)
6UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
7UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
8V3PowerRegulated Power Output (V3 — 3.3V / 5.0V Standard Logic)
9RESET#ISystem Enable & Hardware Reset (RESET#)
10VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
11RXS/RII/OMultiplexed I/O & Peripheral Pin RXS/RI (General)
12TNOW/DCDI/OMultiplexed I/O & Peripheral Pin TNOW/DCD (General)
13GNDGNDGround Reference Pin (GND)
14SUSPEND/DTRI/OMultiplexed I/O & Peripheral Pin SUSPEND/DTR (UART)
15TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
16RTSI/OMultiplexed I/O & Peripheral Pin RTS (UART)
17GNDGNDGround Reference Pin (GND)
PIN 1 VIO
I/O
Multiplexed I/O & Peripheral Pin VIO (General)
Design note: Signal terminal VIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C5187519 (Semiconductor · QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) - 2. Standard Pinout (Top View)
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) - 4. Package Dimensions (D×E×A)
QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1 · 4.00×4.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) - 5. Recommended Land Pattern
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C5187519)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) is a 16-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.64 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.64 mm (25.2 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol17 auto-grouped pins
OK
IPC-7351B Land Pattern17 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 2.60×2.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.65mm
Pad Size (W × L)Level B
0.35 × 0.80 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1)?

Manufactured by Semiconductor, the C5187519 is housed in a QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1 package with 17 pins and a 0.65 mm lead pitch. Key pins include: 1 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 2 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 3 (GND: Ground Reference Pin (GND)), 4 (CTS: Multiplexed I/O & Peripheral Pin CTS (UART)), 5 (TXS/DSR: Multiplexed I/O & Peripheral Pin TXS/DSR (UART)), 6 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)).

What are the IPC-7351B PCB Footprint dimensions for C5187519?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C5187519 (QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.65 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 2.60 × 2.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C5187519?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C5187519 (Semiconductor, QFN-16_L4.0-W4.0-P0.65-TL-EP2.6_1) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (17 pins) & CH9101 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VIODigital_IOSignal terminal VIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
2RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4CTSDigital_IOSignal terminal CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
5TXS/DSRDigital_IOSignal terminal TXS/DSR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXS/DSR. Supported peripheral buses: UART.
6UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
7UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
8V3Power_OutRegulated power output rail (V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
10VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
11RXS/RIDigital_IOSignal terminal RXS/RI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXS/RI. Supported peripheral buses: General.
12TNOW/DCDDigital_IOSignal terminal TNOW/DCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW/DCD. Supported peripheral buses: General.
13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
14SUSPEND/DTRDigital_IOSignal terminal SUSPEND/DTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSPEND/DTR. Supported peripheral buses: UART.
15TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
16RTSDigital_IOSignal terminal RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART.
17GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
ExplorePartsPackagesMFRsUpload