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STM32WB5MMGH6TR (LFLGA-86) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WB5MMGH6TR

STID: C5184586LFLGA-86 · 86 Pins · Pitch 0.45mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WB5MMGH6TR (LFLGA-86)1PA22PA13PA04VREF+5VSS6VDDA7PC38PC29PC110NRST11PB912PC013PH3-BOOT014PB815VBAT16VSS17VDD18PB719PB520PB421PB322PC1023PC1124PC1225PA1326PA1427PA1528PA1029PA1230PA1131VSS32VDDUSB33PD034PD135PB1336PC637PB1438PB1539PB640PC1341PB1242PE443PB086VSS85ANT_NC84VSS83PC882PD1181PD680PD579PE078PE277PD1076PD1575PD874PD973PD472PE371PC770PD369PC968PD267PD766PD1265PD1364PE163PD1462PH161PH060VSS59RF_OUT58ANT_IN57VSS56PA355PA454PA553PA652PA751PA950PA849PC448PB247PB1046PB1145PC544PB1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.861.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586E=7.30mm · Pitch e=0.45mmD=11.00mm-6-5-4-3-2-10123456876543210-1-2-3-4-5-6-7-8mm
3. 3D CAD MODEL
Package Body: 7.30mm × 11.00mm · Pitch: 0.45mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (86/86)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
4VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
5VSSGNDGround Reference Pin (VSS)
6VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
7PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
8PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
10NRSTISystem Enable & Hardware Reset (NRST)
11PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
12PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
13PH3-BOOT0I/OMultiplexed I/O & Peripheral Pin PH3-BOOT0 (General)
14PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
15VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
16VSSGNDGround Reference Pin (VSS)
17VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
18PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
19PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
20PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
21PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
22PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
23PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
24PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
25PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
26PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
27PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
28PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
29PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
30PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
31VSSGNDGround Reference Pin (VSS)
32VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
33PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
34PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
35PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
36PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
37PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
38PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
39PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
40PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
41PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
42PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
43PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
44PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
45PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
46PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
47PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
48PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
49PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
50PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
51PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
52PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
53PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
54PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
55PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
56PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
57VSSGNDExposed Thermal & Ground Pad (VSS)
58ANT_INI/OMultiplexed I/O & Peripheral Pin ANT_IN (General)
59RF_OUTI/OMultiplexed I/O & Peripheral Pin RF_OUT (General)
60VSSGNDGround Reference Pin (VSS)
61PH0I/OMultiplexed I/O & Peripheral Pin PH0 (General)
62PH1I/OMultiplexed I/O & Peripheral Pin PH1 (General)
63PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
64PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
65PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
66PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
67PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
68PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
69PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
70PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
71PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
72PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
73PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
74PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
75PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
76PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
77PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
78PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
79PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
80PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
81PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
82PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
83PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
84VSSGNDGround Reference Pin (VSS)
85ANT_NCI/OMultiplexed I/O & Peripheral Pin ANT_NC (General)
86VSSGNDGround Reference Pin (VSS)
PIN 1 PA2
I/O
Multiplexed I/O & Peripheral Pin PA2 (General)
Design note: Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 22 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WB5MMGH6TR (ST · LFLGA-86)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WB5MMGH6TR (LFLGA-86) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WB5MMGH6TR (LFLGA-86) - 2. Standard Pinout (Top View)
True package pinout (86 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WB5MMGH6TR (LFLGA-86) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WB5MMGH6TR (LFLGA-86) - 4. Package Dimensions (D×E×A)
LFLGA-86 · 7.30×11.00mm · Pitch 0.45mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WB5MMGH6TR (LFLGA-86) - 5. Recommended Land Pattern
IPC-7351B Footprint (86 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WB5MMGH6TR (LFLGA-86) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (22 figures · Page 1/2)
Showing 1–12 of 22 uncropped original figures for STM32WB5MMG / STM32WB5MMGH
P22 · p22_fig01EXACT PACKAGE
STM32WB5MMGH6TR (LFLGA-86) — Figure 14. SiP-LGA86 - Outline
Figure 14. SiP-LGA86 - Outline
P24 · p24_fig01EXACT PACKAGE
STM32WB5MMGH6TR (LFLGA-86) — Figure 15. SiP-LGA86 marking example
Figure 15. SiP-LGA86 marking example
P1 · p01_fig01498×336px
STM32WB5MMGH6TR (LFLGA-86) — These pictures are not contractual
These pictures are not contractual
P1 · p01_fig02268×131px
STM32WB5MMGH6TR (LFLGA-86) — Package dimensions ( mm)
Package dimensions ( mm)
P1 · p01_fig01P1
STM32WB5MMGH6TR (LFLGA-86) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P6 · p06_fig011415×2040px
STM32WB5MMGH6TR (LFLGA-86) — Figure 2. STM32WB5MMG module pinout: bottom view
Figure 2. STM32WB5MMG module pinout: bottom view
P12 · p12_fig011000×468px
STM32WB5MMGH6TR (LFLGA-86) — Figure 6. STM32WB5MMG ground plane layout Tracks
Figure 6. STM32WB5MMG ground plane layout Tracks
P12 · p12_fig02602×318px
STM32WB5MMGH6TR (LFLGA-86) — Figure 6. STM32WB5MMG ground plane layout Tracks
Figure 6. STM32WB5MMG ground plane layout Tracks
P12 · p12_fig03287×327px
STM32WB5MMGH6TR (LFLGA-86) — Figure 7. Sensitive GPIO location
Figure 7. Sensitive GPIO location
P12 · p12_fig04289×330px
STM32WB5MMGH6TR (LFLGA-86) — Figure 7. Sensitive GPIO location
Figure 7. Sensitive GPIO location
P12 · p12_fig05320×333px
STM32WB5MMGH6TR (LFLGA-86) — Figure 7. Sensitive GPIO location
Figure 7. Sensitive GPIO location
P13 · p13_fig011958×2693px
STM32WB5MMGH6TR (LFLGA-86) — DS13252 - Rev 2 page 13/35
DS13252 - Rev 2 page 13/35
Page 1 / 2 (22 extracted figures)

Technical Specifications & Part Details (STM32WB5MMGH6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WB5MMGH6TR (LFLGA-86) is a 86-pin embedded microcontroller unit (mcu) featuring a 11.00 × 7.30 × 1.60 mm mechanical envelope (lead pitch e = 0.45 mm). Rated for 1.8 V to 3.6 V supply operation across -40 °C to 85 °C with integrated Bluetooth / BLE, JTAG / SWD interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40 °C to 85 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
11.00 × 7.30 × 1.60 mm (A1=0.20 mm)
Package family: OTHER (LFLGA-86)
Pin Count & Lead PitchN / e
86 Pins | Pitch e = 0.45 mm (17.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, JTAG / SWD
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol86 auto-grouped pins
OK
IPC-7351B Land Pattern86 pads · Pitch 0.45mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LFLGA-86)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
11.00 × 7.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=0.45mm
Pad Size (W × L)Level B
0.25 × 0.35 mm
Pins / Total PadsTopology
86P / 86Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LFLGA-86
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WB5MMGH6TR (LFLGA-86)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WB5MMGH6TR (LFLGA-86)?

Manufactured by ST, the STM32WB5MMGH6TR is housed in a LFLGA-86 package with 86 pins and a 0.45 mm lead pitch, supporting a VCC supply range of 1.8 V to 3.6 V. Key pins include: 1 (PA2: Multiplexed I/O & Peripheral Pin PA2 (General)), 2 (PA1: Multiplexed I/O & Peripheral Pin PA1 (General)), 3 (PA0: Multiplexed I/O & Peripheral Pin PA0 (General)), 4 (VREF+: Multiplexed I/O & Peripheral Pin VREF+ (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32WB5MMGH6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB5MMGH6TR (LFLGA-86) has a nominal body envelope of 7.30 × 11.00 mm, pitch e = 0.45 mm, and 86 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB5MMGH6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB5MMGH6TR (ST, LFLGA-86) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (86 pins) & STM32WB5MMG / STM32WB5MMGH Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
3PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
4VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
7PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
8PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
10NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
11PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
12PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
13PH3-BOOT0Digital_IOSignal terminal PH3-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3-BOOT0. Supported peripheral buses: General.
14PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
15VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
18PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
19PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
20PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
21PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
22PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
23PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
24PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
25PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
26PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
27PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
28PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
29PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
30PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
34PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
35PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
36PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
37PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
38PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
39PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
40PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
41PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
42PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
43PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
44PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
45PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
46PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
47PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
48PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
49PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
50PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
51PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
52PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
53PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
54PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
55PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
56PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
57VSSGNDBottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
58ANT_INRF_50OhmSignal terminal ANT_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ANT_IN. Supported peripheral buses: General.
59RF_OUTRF_50OhmSignal terminal RF_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF_OUT. Supported peripheral buses: General.
60VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
61PH0Digital_IOSignal terminal PH0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0. Supported peripheral buses: General.
62PH1Digital_IOSignal terminal PH1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1. Supported peripheral buses: General.
63PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
64PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
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