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CH32F205RBT6 (LQFP-64(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32F205RBT6

WCHID: C5158919LQFP-64(10x10) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32F205RBT6 (LQFP-64(10x10))1VBAT2PC13 - TAMPE3PC14 - OSC324PC15 - OSC325OSC_IN6OSC_OUT7NRST8PC09PC110PC211PC3/ADC1312VSSA13VDDA14PA0/WKUP/ADC15PA1/ADC116PA2/ADC217PA3/ADC318VSS_419VDD_420PA4/ADC4/DAC21PA5/ADC5/DAC22PA6/ADC623PA7/ADC724PC4/ADC1425PC5/ADC1526PB0/ADC827PB1/ADC928PB2/BOOT129PB1030PB1131VSS_132VIO_164VIO_363VSS_362PB961PB860BOOT059PB7/USB2DP58PB6/USB2DM57PB556PB455PB354PD253PC1252PC1151PC1050PA1549PA14/SWCLK48VDD_247VSS_246PA13/SWDIO45PA12/USB1DP44PA11/USB1DM43PA1042PA941PA840PC939PC838PC737PC636PB1535PB1434PB1333PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13 - TAMPER RTC(2) -I/OMultiplexed I/O & Peripheral Pin PC13 - TAMPER RTC(2) - (RTC/CLK)
3PC14 - OSC32 IN(2)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(2)_ (RTC/CLK)
4PC15 - OSC32 OUT(2)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)
5OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
6OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
11PC3/ADC13I/OMultiplexed I/O & Peripheral Pin PC3/ADC13 (ADC)
12VSSAGNDGround Reference Pin (VSSA)
13VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
14PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
15PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
16PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
17PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
18VSS_4GNDGround Reference Pin (VSS_4)
19VDD_4PowerPower Supply Input (VDD_4 — 3.3V / 5.0V Standard Logic)
20PA4/ADC4/DAC0I/OMultiplexed I/O & Peripheral Pin PA4/ADC4/DAC0 (ADC, DAC)
21PA5/ADC5/DAC1I/OMultiplexed I/O & Peripheral Pin PA5/ADC5/DAC1 (ADC, DAC)
22PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
23PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
24PC4/ADC14I/OMultiplexed I/O & Peripheral Pin PC4/ADC14 (ADC)
25PC5/ADC15I/OMultiplexed I/O & Peripheral Pin PC5/ADC15 (ADC)
26PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
27PB1/ADC9I/OMultiplexed I/O & Peripheral Pin PB1/ADC9 (ADC)
28PB2/BOOT1I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
30PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
31VSS_1GNDGround Reference Pin (VSS_1)
32VIO_1I/OMultiplexed I/O & Peripheral Pin VIO_1 (General)
33PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
34PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
35PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
36PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
37PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
38PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
39PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
40PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
41PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
42PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
43PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
44PA11/USB1DMI/OMultiplexed I/O & Peripheral Pin PA11/USB1DM (USB)
45PA12/USB1DPI/OMultiplexed I/O & Peripheral Pin PA12/USB1DP (USB)
46PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
47VSS_2GNDGround Reference Pin (VSS_2)
48VDD_2PowerPower Supply Input (VDD_2 — 3.3V / 5.0V Standard Logic)
49PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
50PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
51PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
52PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
53PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
54PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
55PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
56PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
57PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
58PB6/USB2DMI/OMultiplexed I/O & Peripheral Pin PB6/USB2DM (USB)
59PB7/USB2DPI/OMultiplexed I/O & Peripheral Pin PB7/USB2DP (USB)
60BOOT0IInput-Only Pin BOOT0 (General)
61PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
62PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
63VSS_3GNDGround Reference Pin (VSS_3)
64VIO_3I/OMultiplexed I/O & Peripheral Pin VIO_3 (General)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32F205RBT6 (WCH · LQFP-64(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32F205RBT6 (LQFP-64(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32F205RBT6 (LQFP-64(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32F205RBT6 (LQFP-64(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32F205RBT6 (LQFP-64(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32F205RBT6 (LQFP-64(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32F205RBT6 (LQFP-64(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for CH32F205 / CH32F207
P85 · p85_fig02EXACT PACKAGE
CH32F205RBT6 (LQFP-64(10x10)) — Figure 5-5 LQFP64M outline
Figure 5-5 LQFP64M outline
P1 · p01_fig01246×133px
CH32F205RBT6 (LQFP-64(10x10)) — Overview
Overview
P22 · p22_fig011438×1512px
CH32F205RBT6 (LQFP-64(10x10)) — PA14/SWCLK 49 PA15 50 PC10 51 PC11 52 PC12 53 PD2 54 PB3 55 PB4 56 PB5 57 PB6/USB2DM 58 PB7/USB2DP 59 BOOT0 60 PB8 61 PB9 62 VSS_3 63 VIO_3 64
PA14/SWCLK 49 PA15 50 PC10 51 PC11 52 PC12 53 PD2 54 PB3 55 PB4 56 PB5 57 PB6/USB2DM 58 PB7/USB2DP 59 BOOT0 60 PB8 61 PB9 62 VSS_3 63 VIO_3 64
P22 · p22_fig02935×936px
CH32F205RBT6 (LQFP-64(10x10)) — CH32F205RBT6
CH32F205RBT6
P22 · p22_fig01P22
CH32F205RBT6 (LQFP-64(10x10)) — Datasheet Page 22 (p22_fig01)
Datasheet Page 22 (p22_fig01)
P53 · p53_fig011852×794px
CH32F205RBT6 (LQFP-64(10x10)) — CH32F20x Datasheet 50 http://wch.cn
CH32F20x Datasheet 50 http://wch.cn
P53 · p53_fig01P53
CH32F205RBT6 (LQFP-64(10x10)) — Datasheet Page 53 (p53_fig01)
Datasheet Page 53 (p53_fig01)
P79 · p79_fig011852×1083px
CH32F205RBT6 (LQFP-64(10x10)) — R < Ts f × C × ln 2 -R
R < Ts f × C × ln 2 -R
P79 · p79_fig01P79
CH32F205RBT6 (LQFP-64(10x10)) — Datasheet Page 79 (p79_fig01)
Datasheet Page 79 (p79_fig01)
P84 · p84_fig01811×615px
CH32F205RBT6 (LQFP-64(10x10)) — Figure 5-1 QFN48X7 outline
Figure 5-1 QFN48X7 outline
P84 · p84_fig02811×615px
CH32F205RBT6 (LQFP-64(10x10)) — Figure 5-2 QFN68X8 outline
Figure 5-2 QFN68X8 outline
P84 · p84_fig01P84
CH32F205RBT6 (LQFP-64(10x10)) — Datasheet Page 84 (p84_fig01)
Datasheet Page 84 (p84_fig01)
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (CH32F205RBT6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32F205RBT6 (LQFP-64(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
144MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH32F205 / CH32F207 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (LQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32F205RBT6 (LQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32F205RBT6 (LQFP-64(10x10))?

Manufactured by WCH, the CH32F205RBT6 is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13 - TAMPER RTC(2) -: Multiplexed I/O & Peripheral Pin PC13 - TAMPER RTC(2) - (RTC/CLK)), 3 (PC14 - OSC32 IN(2)_: Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(2)_ (RTC/CLK)), 4 (PC15 - OSC32 OUT(2)_: Multiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)), 5 (OSC_IN: Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)), 6 (OSC_OUT: Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32F205RBT6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32F205RBT6 (LQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32F205RBT6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32F205RBT6 (WCH, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH32F205 / CH32F207 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13 - TAMPER RTC(2) -Digital_IOSignal terminal PC13 - TAMPER RTC(2) - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13 - TAMPER RTC(2) -. Supported peripheral buses: RTC/CLK.
3PC14 - OSC32 IN(2)_Digital_IOSignal terminal PC14 - OSC32 IN(2)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14 - OSC32 IN(2)_. Supported peripheral buses: RTC/CLK.
4PC15 - OSC32 OUT(2)_Digital_IOSignal terminal PC15 - OSC32 OUT(2)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15 - OSC32 OUT(2)_. Supported peripheral buses: RTC/CLK.
5OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
6OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
11PC3/ADC13AnalogSignal terminal PC3/ADC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3/ADC13. Supported peripheral buses: ADC.
12VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
15PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
16PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
17PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
18VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
19VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20PA4/ADC4/DAC0AnalogSignal terminal PA4/ADC4/DAC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ADC4/DAC0. Supported peripheral buses: ADC, DAC.
21PA5/ADC5/DAC1AnalogSignal terminal PA5/ADC5/DAC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5/DAC1. Supported peripheral buses: ADC, DAC.
22PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
23PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
24PC4/ADC14AnalogSignal terminal PC4/ADC14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/ADC14. Supported peripheral buses: ADC.
25PC5/ADC15AnalogSignal terminal PC5/ADC15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/ADC15. Supported peripheral buses: ADC.
26PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
27PB1/ADC9AnalogSignal terminal PB1/ADC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC.
28PB2/BOOT1Digital_IOSignal terminal PB2/BOOT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
30PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
31VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
32VIO_1Digital_IOSignal terminal VIO_1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_1. Supported peripheral buses: General.
33PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
34PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
35PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
36PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
37PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
38PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
39PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
40PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
41PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
42PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
43PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
44PA11/USB1DMDigital_IOSignal terminal PA11/USB1DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/USB1DM. Supported peripheral buses: USB.
45PA12/USB1DPDigital_IOSignal terminal PA12/USB1DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/USB1DP. Supported peripheral buses: USB.
46PA13/SWDIODigital_IOSignal terminal PA13/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG.
47VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
50PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
51PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
52PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
53PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
54PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
55PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
56PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
57PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
58PB6/USB2DMDigital_IOSignal terminal PB6/USB2DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/USB2DM. Supported peripheral buses: USB.
59PB7/USB2DPDigital_IOSignal terminal PB7/USB2DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/USB2DP. Supported peripheral buses: USB.
60BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
62PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
63VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
64VIO_3Digital_IOSignal terminal VIO_3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_3. Supported peripheral buses: General.
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